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la-machxo automotive family data sheet ds1003 version 01.5, november 2007
april 2006 data sheet ds1003 ?2006 lattice semiconductor corp. all lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www .latticesemi.com/legal. all other brand or product names are trademarks or registered trademarks of their respective holders. the speci?ations and information herein are subject to change without notice. www.latticesemi.com 1-1 ds1003 introduction_01.0 features non-volatile, in?itely recon?urable instant-on ?powers up in microseconds single chip, no external con?uration memory required excellent design security, no bit stream to intercept recon?ure sram based logic in milliseconds sram and non-volatile memory programmable through jtag port supports background programming of non-volatile memory aec-q100 tested and quali?d sleep mode allows up to 100x static current reduction transfr recon?uration (tfr) in-?ld logic update while system operates high i/o to logic density 256 to 2280 lut4s 73 to 271 i/os with extensive package options density migration supported lead free/rohs compliant packaging embedded and distributed memory up to 27.6 kbits sysmem embedded block ram up to 7.5 kbits distributed ram dedicated fifo control logic flexible i/o buffer programmable sysio buffer supports wide range of interfaces: ? lvcmos 3.3/2.5/1.8/1.5/1.2 ? lvttl ? pci ? lvds, bus-lvds, lvpecl, rsds sysclock plls up to two analog plls per device clock multiply, divide, and phase shifting system level support ieee standard 1149.1 boundary scan onboard oscillator devices operate with 3.3v, 2.5v, 1.8v or 1.2v power supply ieee 1532 compliant in-system programming introduction the la-machxo automotive device family is optimized to meet the requirements of applications traditionally addressed by cplds and low capacity fpgas: glue logic, bus bridging, bus interfacing, power-up control, and control logic. these devices bring together the best features of cpld and fpga devices on a single chip in aec-q100 tested and quali?d versions. the devices use look-up tables (luts) and embedded block memories traditionally associated with fpgas for ?xible and ef?ient logic implementation. through non- volatile technology, the devices provide the single-chip, table 1-1. la-machxo automotive family selection guide device lamxo256e/c lamxo640e/c lamxo1200e lamxo2280e luts 256 640 1200 2280 dist. ram (kbits) 2.0 6.0 6.25 7.5 ebr sram (kbits) 0 0 9.2 27.6 number of ebr sram blocks (9 kbits) 0013 v cc voltage 1.2/1.8/2.5/3.3v 1.2/1.8/2.5/3.3v 1.2 1.2 number of plls 0012 max. i/o 78 159 211 271 packages 100-pin lead-free tqfp (14x14 mm) 78 74 73 73 144-pin lead-free tqfp (20x20 mm) 113 113 113 256-ball lead-free ftbga (17x17 mm) 159 211 211 324-ball lead-free ftbga (19x19 mm) 271 la-machxo automotive family data sheet introduction
introduction lattice semiconductor la-machxo automotive family data sheet 1-2 high-security, instant-on capabilities traditionally associated with cplds. finally, advanced process technology and careful design will provide the high pin-to-pin performance also associated with cplds. the isplever design tools from lattice allow complex designs to be ef?iently implemented using the la- machxo automotive family of devices. popular logic synthesis tools provide synthesis library support for la- machxo. the isplever tools use the synthesis tool output along with the constraints from its ?or planning tools to place and route the design in the la-machxo device. the isplever tool extracts the timing from the routing and back-annotates it into the design for timing veri?ation.
february 2007 data sheet ds1003 ?2007 lattice semiconductor corp. all lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www .latticesemi.com/legal. all other brand or product names are trademarks or registered trademarks of their respective holders. the speci?ations and information herein are subject to change without notice. www.latticesemi.com 2-1 ds1003 architecture_01.2 architecture overview the la-machxo family architecture contains an array of logic blocks surrounded by programmable i/o (pio). some devices in this family have sysclock plls and blocks of sysmem embedded block ram (ebrs). fig- ures 2-1, 2-2, and 2-3 show the block diagrams of the various family members. the logic blocks are arranged in a two-dimensional grid with rows and columns. the ebr blocks are arranged in a column to the left of the logic array. the pio cells are located at the periphery of the device, arranged into banks. the pios utilize a ?xible i/o buffer referred to as a sysio interface that supports operation with a variety of inter- face standards. the blocks are connected with many vertical and horizontal routing channel resources. the place and route software tool automatically allocates these routing resources. there are two kinds of logic blocks, the programmable functional unit (pfu) and the programmable functional unit without ram (pff). the pfu contains the building blocks for logic, arithmetic, ram, rom, and register func- tions. the pff block contains building blocks for logic, arithmetic, rom, and register functions. both the pfu and pff blocks are optimized for ?xibility, allowing complex designs to be implemented quickly and effectively. logic blocks are arranged in a two-dimensional array. only one type of block is used per row. in the la-machxo family, the number of sysio banks varies by device. there are different types of i/o buffers on different banks. see the details in later sections of this document. the sysmem ebrs are large, dedicated fast memory blocks; these blocks are found only in the larger devices. these blocks can be con?ured as ram, rom or fifo. fifo support includes dedicated fifo pointer and ?g ?ard control logic to minimize lut use. the la-machxo architecture provides up to two sysclock phase locked loop (pll) blocks on larger devices. these blocks are located at either end of the memory blocks. the plls have multiply, divide, and phase shifting capabilities that are used to manage the frequency and phase relationships of the clocks. every device in the family has a jtag port that supports programming and con?uration of the device as well as access to the user logic. the la-machxo devices are available for operation from 3.3v, 2.5v, 1.8v, and 1.2v power supplies, providing easy integration into the overall system. la-machxo automotive family data sheet architecture
2-2 architecture lattice semiconductor la-machxo automotive family data sheet figure 2-1. top view of the la-machxo1200 device 1 1. top view of the la-machxo2280 device is similar but with higher lut count, two plls, and three ebr blocks. figure 2-2. top view of the la-machxo640 device jtag port programmable functional units without ram (pffs) programmable functional units with ram (pfus) pios arranged into sysio banks sysmem embedded block ram (ebr) sysclock pll jtag port pios arranged into sysio banks programmable function units with ram (pfus) programmable function units without ram (pffs)
2-3 architecture lattice semiconductor la-machxo automotive family data sheet figure 2-3. top view of the la-machxo256 device pfu blocks the core of the la-machxo devices consists of pfu and pff blocks. the pfus can be programmed to perform logic, arithmetic, distributed ram, and distributed rom functions. pff blocks can be programmed to perform logic, arithmetic, and distributed rom functions. except where necessary, the remainder of this data sheet will use the term pfu to refer to both pfu and pff blocks. each pfu block consists of four interconnected slices, numbered 0-3 as shown in figure 2-4. there are 53 inputs and 25 outputs associated with each pfu block. figure 2-4. pfu diagram slice each slice contains two lut4 lookup tables feeding two registers (programmed to be in ff or latch mode), and some associated logic that allows the luts to be combined to perform functions such as lut5, lut6, lut7, and lut8. there is control logic to perform set/reset functions (programmable as synchronous/asynchronous), clock select, chip-select, and wider ram/rom functions. figure 2-5 shows an overview of the internal logic of the slice. the registers in the slice can be con?ured for positive/negative and edge/level clocks. jtag port programmable function units with ram (pfus) programmable function units without ram (pffs) pios arranged into sysio banks slice 0 lut4 & carry lut4 & carry ff/ latch fcin fco d ff/ latch d slice 1 lut4 & carry lut4 & carry slice 2 lut4 & carry lut4 & carry from routing to routing slice 3 lut4 & carry lut4 & carry ff/ latch d ff/ latch d ff/ latch d ff/ latch d ff/ latch d ff/ latch d
2-4 architecture lattice semiconductor la-machxo automotive family data sheet there are 14 input signals: 13 signals from routing and one from the carry-chain (from the adjacent slice/pfu). there are 7 outputs: 6 to the routing and one to the carry-chain (to the adjacent slice/pfu). table 2-1 lists the sig- nals associated with each slice. figure 2-5. slice diagram table 2-1. slice signal descriptions function type signal names description input data signal a0, b0, c0, d0 inputs to lut4 input data signal a1, b1, c1, d1 inputs to lut4 input multi-purpose m0/m1 multipurpose input input control signal ce clock enable input control signal lsr local set/reset input control signal clk system clock input inter-pfu signal fcin fast carry in 1 output data signals f0, f1 lut4 output register bypass signals output data signals q0, q1 register outputs output data signals ofx0 output of a lut5 mux output data signals ofx1 output of a lut6, lut7, lut8 2 mux depending on the slice output inter-pfu signal fco fast carry out 1 1. see figure 2-4 for connection details. 2. requires two pfus. lut4 & carry lut4 & carry slice a0 b0 c0 d0 ff/ latch ofx0 f0 q0 a1 b1 c1 d1 ci ci co co f sum ce clk lsr ff/ latch ofx1 f1 q1 fast connection to i/o cell* f sum d d m1 from adjacent slice/pfu to adjacent slice/pfu fast connection to i/o cell* lut expansion mux m0 ofx0 from routing to routing control signals selected and inverted per slice in routing notes: some inter-slice signals are not shown. * only pfus at the edges have fast connections to the i/o cell.
2-5 architecture lattice semiconductor la-machxo automotive family data sheet modes of operation each slice is capable of four modes of operation: logic, ripple, ram, and rom. the slice in the pff is capable of all modes except ram. table 2-2 lists the modes and the capability of the slice blocks. table 2-2. slice modes logic mode: in this mode, the luts in each slice are con?ured as 4-input combinatorial lookup tables (lut4). a lut4 can have 16 possible input combinations. any logic function with four inputs can be generated by program- ming this lookup table. since there are two lut4s per slice, a lut5 can be constructed within one slice. larger lookup tables such as lut6, lut7, and lut8 can be constructed by concatenating other slices. ripple mode: ripple mode allows the ef?ient implementation of small arithmetic functions. in ripple mode, the fol- lowing functions can be implemented by each slice: addition 2-bit subtraction 2-bit add/subtract 2-bit using dynamic control up counter 2-bit down counter 2-bit ripple mode multiplier building block comparator functions of a and b inputs - a greater-than-or-equal-to b - a not-equal-to b - a less-than-or-equal-to b two additional signals, carry generate and carry propagate, are generated per slice in this mode, allowing fast arithmetic functions to be constructed by concatenating slices. ram mode: in this mode, distributed ram can be constructed using each lut block as a 16x2-bit memory. through the combination of luts and slices, a variety of different memories can be constructed. the isplever design tool supports the creation of a variety of different size memories. where appropriate, the software will construct these using distributed memory primitives that represent the capabilities of the pfu. table 2-3 shows the number of slices required to implement different distributed ram primitives. figure 2-6 shows the distributed memory primitive block diagrams. dual port memories involve the pairing of two slices. one slice functions as the read-write port, while the other companion slice supports the read-only port. for more information on ram mode in la-machxo devices, please see details of additional technical documentation at the end of this data sheet. table 2-3. number of slices required for implementing distributed ram logic ripple ram rom pfu slice lut 4x2 or lut 5x1 2-bit arithmetic unit sp 16x2 rom 16x1 x 2 pff slice lut 4x2 or lut 5x1 2-bit arithmetic unit n/a rom 16x1 x 2 spr16x2 dpr16x2 number of slices 1 2 note: spr = single port ram, dpr = dual port ram
2-6 architecture lattice semiconductor la-machxo automotive family data sheet figure 2-6. distributed memory primitives rom mode: the rom mode uses the same principal as the ram modes, but without the write port. pre-loading is accomplished through the programming interface during con?uration. pfu modes of operation slices can be combined within a pfu to form larger functions. table 2-4 tabulates these modes and documents the functionality possible at the pfu level. table 2-4. pfu modes of operation routing there are many resources provided in the la-machxo devices to route signals individually or as buses with related control signals. the routing resources consist of switching circuitry, buffers and metal interconnect (routing) segments. the inter-pfu connections are made with three different types of routing resources: x1 (spans two pfus), x2 (spans three pfus) and x6 (spans seven pfus). the x1, x2, and x6 connections provide fast and ef?ient connec- tions in the horizontal and vertical directions. logic ripple ram rom lut 4x8 or mux 2x1 x 8 2-bit add x 4 spr16x2 x 4 dpr16x2 x 2 rom16x1 x 8 lut 5x4 or mux 4x1 x 4 2-bit sub x 4 spr16x4 x 2 dpr16x4 x 1 rom16x2 x 4 lut 6x 2 or mux 8x1 x 2 2-bit counter x 4 spr16x8 x 1 rom16x4 x 2 lut 7x1 or mux 16x1 x 1 2-bit comp x 4 rom16x8 x 1 do1 do0 di0 di1 ad0 ad1 ad2 ad3 wre ck do0 ad0 ad1 ad2 ad3 dpr16x2 spr16x2 rom16x1 rdo1 rdo0 di0 di1 wck wre wdo1 wdo0 wad0 wad1 wad2 wad3 rad0 rad1 rad2 rad3
2-7 architecture lattice semiconductor la-machxo automotive family data sheet the isplever design tool takes the output of the synthesis tool and places and routes the design. generally, the place and route tool is completely automatic, although an interactive routing editor is available to optimize the design. clock/control distribution network the la-machxo automotive family of devices provides global signals that are available to all pfus. these signals consist of four primary clocks and four secondary clocks. primary clock signals are generated from four 16:1 muxes as shown in figure 2-7 and figure 2-8. the available clock sources for the la-machxo256 and la-machxo640 devices are four dual function clock pins and 12 internal routing signals. the available clock sources for the la- machxo1200 and la-machxo2280 devices are four dual function clock pins, up to nine internal routing signals and up to six pll outputs. figure 2-7. primary clocks for la-machxo256 and la-machxo640 devices ro u ting clock pads primary clock 0 primary clock 1 primary clock 2 primary clock 3 4 12 16:1 16:1 16:1 16:1
2-8 architecture lattice semiconductor la-machxo automotive family data sheet figure 2-8. primary clocks for la-machxo1200 and la-machxo2280 devices four secondary clocks are generated from four 16:1 muxes as shown in figure 2-9. four of the secondary clock sources come from dual function clock pins and 12 come from internal routing. figure 2-9. secondary clocks for la-machxo devices pll o u tp u ts ro u ting clock pads primary clock 0 primary clock 1 primary clock 2 primary clock 3 4 up to 9 up to 6 16:1 16:1 16:1 16:1 ro u ting clock pads secondary (control) clocks 4 12 16:1 16:1 16:1 16:1
2-9 architecture lattice semiconductor la-machxo automotive family data sheet sysclock phase locked loops (plls) the la-machxo1200 and la-machxo2280 provide pll support. the source of the pll input divider can come from an external pin or from internal routing. there are four sources of feedback signals to the feedback divider: from clkintfb (internal feedback port), from the global clock nets, from the output of the post scalar divider, and from the routing (or from an external pin). there is a pll_lock signal to indicate that the pll has locked on to the input clock signal. figure 2-10 shows the sysclock pll diagram. the setup and hold times of the device can be improved by programming a delay in the feedback or input path of the pll which will advance or delay the output clock with reference to the input clock. this delay can be either pro- grammed during con?uration or can be adjusted dynamically. in dynamic mode, the pll may lose lock after adjustment and not relock until the t lock parameter has been satis?d. additionally, the phase and duty cycle block allows the user to adjust the phase and duty cycle of the clkos output. the sysclock plls provide the ability to synthesize clock frequencies. each pll has four dividers associated with it: input clock divider, feedback divider, post scalar divider, and secondary clock divider. the input clock divider is used to divide the input clock signal, while the feedback divider is used to multiply the input clock signal. the post scalar divider allows the vco to operate at higher frequencies than the clock output, thereby increasing the fre- quency range. the secondary divider is used to derive lower frequency outputs. figure 2-10. pll diagram figure 2-11 shows the available macros for the pll. table 2-5 provides signal description of the pll block. figure 2-11. pll primitive vco clkos clkok clkintfb (internal feedback) lock rst clkfb (from post scalar divider output, clock net, routing/external pin or clkintfb port dynamic delay adjustment input clock divider (clki) feedback divider (clkfb) post scalar divider (clkop) phase/duty select secondary clock divider (clkok) delay adjust voltage controlled oscillator clki (from routing or external pin) clkop ehxpllc clkos clki clkfb clkok lock rst clkop ddaizr ddailag dda mode ddaidel[2:0] clkintfb
2-10 architecture lattice semiconductor la-machxo automotive family data sheet table 2-5. pll signal descriptions for more information on the pll, please see details of additional technical documentation at the end of this data sheet. sysmem memory the la-machxo1200 and la-machxo2280 devices contain sysmem embedded block rams (ebrs). the ebr consists of a 9-kbit ram, with dedicated input and output registers. sysmem memory block the sysmem block can implement single port, dual port, pseudo dual port, or fifo memories. each block can be used in a variety of depths and widths as shown in table 2-6. table 2-6. sysmem block con?urations signal i/o description clki i clock input from external pin or routing clkfb i pll feedback input from pll output, clock net, routing/external pin or internal feedback from clkintfb port rst i ? to reset the input clock divider clkos o pll output clock to clock tree (phase shifted/duty cycle changed) clkop o pll output clock to clock tree (no phase shift) clkok o pll output to clock tree through secondary clock divider lock o ? indicates pll lock to clki clkintfb o internal feedback source, clkop divider output before clocktree ddamode i dynamic delay enable. ?? pin control (dynamic), ?? fuse control (static) ddaizr i dynamic delay zero. ?? delay = 0, ?? delay = on ddailag i dynamic delay lag/lead. ?? lag, ?? lead ddaidel[2:0] i dynamic delay input memory mode con?urations single port 8,192 x 1 4,096 x 2 2,048 x 4 1,024 x 9 512 x 18 256 x 36 true dual port 8,192 x 1 4,096 x 2 2,048 x 4 1,024 x 9 512 x 18 pseudo dual port 8,192 x 1 4,096 x 2 2,048 x 4 1,024 x 9 512 x 18 256 x 36 fifo 8,192 x 1 4,096 x 2 2,048 x 4 1,024 x 9 512 x 18 256 x 36
2-11 architecture lattice semiconductor la-machxo automotive family data sheet bus size matching all of the multi-port memory modes support different widths on each of the ports. the ram bits are mapped lsb word 0 to msb word 0, lsb word 1 to msb word 1 and so on. although the word size and number of words for each port varies, this mapping scheme applies to each port. ram initialization and rom operation if desired, the contents of the ram can be pre-loaded during device con?uration. by preloading the ram block during the chip con?uration cycle and disabling the write controls, the sysmem block can also be utilized as a rom. memory cascading larger and deeper blocks of rams can be created using ebr sysmem blocks. typically, the lattice design tools cascade memory transparently, based on speci? design inputs. single, dual, pseudo-dual port and fifo modes figure 2-12 shows the ?e basic memory con?urations and their input/output names. in all the sysmem ram modes, the input data and address for the ports are registered at the input of the memory array. the output data of the memory is optionally registered at the memory array output. figure 2-12. sysmem memory primitives ebr ad[12:0] di[35:0] clk ce rst we cs[2:0] do[35:0] single port ram ebr true dual port ram pseudo-dual port ram rom ad[12:0] clk ce do[35:0] rst cs[2:0] ebr ebr ada[12:0] dia[17:0] clka cea rsta wea csa[2:0] doa[17:0] adb[12:0] dib[17:0] clkb ceb rstb web csb[2:0] dob[17:0] adw[12:0] di[35:0] clkw cew adr[12:0] do[35:0] cer clkr we rst cs[2:0] fifo ebr di[35:0] clkw rsta do[35:0] clkr rstb re rce ff af ef ae we cew
2-12 architecture lattice semiconductor la-machxo automotive family data sheet the ebr memory supports three forms of write behavior for single or dual port operation: 1. normal ?data on the output appears only during the read cycle. during a write cycle, the data (at the current address) does not appear on the output. this mode is supported for all data widths. 2. write through ?a copy of the input data appears at the output of the same port. this mode is supported for all data widths. 3. read-before-write ?when new data is being written, the old contents of the address appears at the output. this mode is supported for x9, x18 and x36 data widths. fifo con?uration the fifo has a write port with data-in, cew, we and clkw signals. there is a separate read port with data-out, rce, re and clkr signals. the fifo internally generates almost full, full, almost empty and empty flags. the full and almost full ?gs are registered with clkw. the empty and almost empty ?gs are registered with clkr. the range of programming values for these ?gs are in table 2-7. table 2-7. programmable fifo flag ranges the fifo state machine supports two types of reset signals: rsta and rstb. the rsta signal is a global reset that clears the contents of the fifo by resetting the read/write pointer and puts the fifo ?gs in their initial reset state. the rstb signal is used to reset the read pointer. the purpose of this reset is to retransmit the data that is in the fifo. in these applications it is important to keep careful track of when a packet is written into or read from the fifo. memory core reset the memory array in the ebr utilizes latches at the a and b output ports. these latches can be reset asynchro- nously. rsta and rstb are local signals, which reset the output latches associated with port a and port b respec- tively. the global reset (gsrn) signal resets both ports. the output data latches and associated resets for both ports are as shown in figure 2-13. flag name programming range full (ff) 1 to (up to 2 n -1) almost full (af) 1 to full-1 almost empty (ae) 1 to full-1 empty (ef) 0 n = address bit width
2-13 architecture lattice semiconductor la-machxo automotive family data sheet figure 2-13. memory core reset for further information on the sysmem ebr block, see the details of additional technical documentation at the end of this data sheet. ebr asynchronous reset ebr asynchronous reset or gsr (if used) can only be applied if all clock enables are low for a clock cycle before the reset is applied and released a clock cycle after the reset is released, as shown in figure 2-14. the gsr input to the ebr is always asynchronous. figure 2-14. ebr asynchronous reset (including gsr) timing diagram if all clock enables remain enabled, the ebr asynchronous reset or gsr may only be applied and released after the ebr read and write clock inputs are in a steady state condition for a minimum of 1/f max (ebr clock). the reset release must adhere to the ebr synchronous reset setup time before the next active read or write clock edge. if an ebr is pre-loaded during con?uration, the gsr input must be disabled or the release of the gsr during device wake up must occur before the release of the device i/os becoming active. these instructions apply to all ebr ram, rom and fifo implementations. for the ebr fifo mode, the gsr sig- nal is always enabled and the we and re signals act like the clock enable signals in figure 2-14. the reset timing rules apply to the rpreset input vs the re input and the rst input vs. the we and re inputs. both rst and rpreset are always asynchronous ebr inputs. note that there are no reset restrictions if the ebr synchronous reset is used and the ebr gsr input is disabled. q set d l clr output data latches memory core port a[17:0] q set d port b[17:0] rstb gsrn programmable disable rsta l clr reset clock clock ena b le
2-14 architecture lattice semiconductor la-machxo automotive family data sheet pio groups on the la-machxo devices, pio cells are assembled into two different types of pio groups, those with four pio cells and those with six pio cells. pio groups with four ios are placed on the left and right sides of the device while pio groups with six ios are placed on the top and bottom. the individual pio cells are connected to their respec- tive sysio buffers and pads. on all la-machxo devices, two adjacent pios can be joined to provide a complementary output driver pair. the i/ o pin pairs are labeled as "t" and "c" to distinguish between the true and complement pins. the la-machxo1200 and la-machxo2280 devices contain enhanced i/o capability. all pio pairs on these larger devices can implement differential receivers. in addition, half of the pio pairs on the left and right sides of these devices can be con?ured as lvds transmit/receive pairs. pios on the top of these larger devices also provide pci support. figure 2-15. group of four programmable i/o cells figure 2-16. group of six programmable i/o cells pio the pio blocks provide the interface between the sysio buffers and the internal pfu array blocks. these blocks receive output data from the pfu array and a fast output data signal from adjacent pfus. the output data and fast pio b pio c pio d pio a pada "t" padb "c" padc "t" padd "c" four pios this structure is used on the left and right of machxo devices pio b pio c pio d pio a pada "t" padb "c" padc "t" padd "c" six pios pio e pio f pade "t" padf "c" this structure is used on the top and bottom of machxo devices
2-15 architecture lattice semiconductor la-machxo automotive family data sheet output data signals are multiplexed and provide a single signal to the i/o pin via the sysio buffer. figure 2-17 shows the la-machxo pio logic. the tristate control signal is multiplexed from the output data signals and their complements. in addition a global signal (tsall) from a dedicated pad can be used to tristate the sysio buffer. the pio receives an input signal from the pin via the sysio buffer and provides this signal to the core of the device. in addition there are programmable elements that can be utilized by the design tools to avoid positive hold times. figure 2-17. la-machxo pio block diagram sysio buffer each i/o is associated with a ?xible buffer referred to as a sysio buffer. these buffers are arranged around the periphery of the device in groups referred to as banks. the sysio buffers allow users to implement the wide variety of standards that are found in todays systems including lvcmos, ttl, blvds, lvds and lvpecl. in the la-machxo devices, single-ended output buffers and ratioed input buffers (lvttl, lvcmos and pci) are powered using v ccio . in addition to the bank v ccio supplies, the la-machxo devices have a v cc core logic power supply, and a v ccaux supply that powers up a variety of internal circuits including all the differential and referenced input buffers. la-machxo256 and la-machxo640 devices contain single-ended input buffers and single-ended output buffers with complementary outputs on all the i/o banks. la-machxo1200 and la-machxo2280 devices contain two types of sysio buffer pairs. 1. top and bottom sysio buffer pairs the sysio buffer pairs in the top and bottom banks of the device consist of two single-ended output drivers and two sets of single-ended input buffers (for ratioed or absolute input levels). the i/o pairs on the top and bottom pad sysio b u ffer to programma b le delay elements from complementary pad 1 2 3 4 + - inp u t data signal from ro u ting from ro u ting fast o u tp u t n ote: b u ffer 1 tracks w ith v ccaux b u ffer 3 tracks w ith internal 1.2 v v ref . b u ffer 4 is a v aila b le in machxo1200 and machxo22 8 0 de v ices only. b u ffer 2 tracks w ith v ccio. data signal tsall do ts
2-16 architecture lattice semiconductor la-machxo automotive family data sheet of the devices also support differential input buffers. pci clamps are available on the top bank i/o buffers. the pci clamp is enabled after v cc , v ccaux , and v ccio are at valid operating levels and the device has been con- ?ured. the two pads in the pair are described as ?rue and ?omp? where the true pad is associated with the positive side of the differential input buffer and the comp (complementary) pad is associated with the negative side of the differential input buffer. 2. left and right sysio buffer pairs the sysio buffer pairs in the left and right banks of the device consist of two single-ended output drivers and two sets of single-ended input buffers (supporting ratioed and absolute input levels). the devices also have a differential driver per output pair. the referenced input buffer can also be con?ured as a differential input buffer. in these banks the two pads in the pair are described as ?rue and ?omp? where the true pad is asso- ciated with the positive side of the differential i/o, and the comp (complementary) pad is associated with the negative side of the differential i/o. typical i/o behavior during power-up the internal power-on-reset (por) signal is deactivated when v cc and v ccaux have reached satisfactory levels. after the por signal is deactivated, the fpga core logic becomes active. it is the users responsibility to ensure that all v ccio banks are active with valid input logic levels to properly control the output logic states of all the i/o banks that are critical to the application. the default con?uration of the i/o pins in a blank device is tri-state with a weak pull-up to vccio. the i/o pins will maintain the blank con?uration until vcc, vccaux and vccio have reached satisfactory levels at which time the i/os will take on the user-con?ured settings. the v cc and v ccaux supply the power to the fpga core fabric, whereas the v ccio supplies power to the i/o buff- ers. in order to simplify system design while providing consistent and predictable i/o behavior, the i/o buffers should be powered up along with the fpga core fabric. therefore, v ccio supplies should be powered up before or together with the v cc and v ccaux supplies supported standards the la-machxo sysio buffer supports both single-ended and differential standards. single-ended standards can be further subdivided into lvcmos and lvttl. the buffer supports the lvttl, lvcmos 1.2, 1.5, 1.8, 2.5, and 3.3v standards. in the lvcmos and lvttl modes, the buffer has individually con?urable options for drive strength, bus maintenance (weak pull-up, weak pull-down, bus-keeper latch or none) and open drain. blvds and lvpecl output emulation is supported on all devices. the la-machxo1200 and la-machxo2280 support on-chip lvds output buffers on approximately 50% of the i/os on the left and right banks. differential receivers for lvds, blvds and lvpecl are supported on all banks of la-machxo1200 and la-machxo2280 devices. pci support is provided in the top banks of the la-machxo1200 and la-machxo2280 devices. table 2-8 summarizes the i/o characteristics of the devices in the la-machxo family. tables 2-9 and 2-10 show the i/o standards (together with their supply and reference voltages) supported by the la-machxo devices. for further information on utilizing the sysio buffer to support a variety of standards please see the details of additional technical documentation at the end of this data sheet.
2-17 architecture lattice semiconductor la-machxo automotive family data sheet table 2-8. i/o support device by device table 2-9. supported input standards la-machxo256 la-machxo640 la-machxo1200 la-machxo2280 number of i/o banks 2488 type of input buffers single-ended (all i/o banks) single-ended (all i/o banks) single-ended (all i/o banks) differential receivers (all i/o banks) single-ended (all i/o banks) differential receivers (all i/o banks) types of output buffers single-ended buffers with complementary outputs (all i/o banks) single-ended buffers with complementary outputs (all i/o banks) single-ended buffers with complementary outputs (all i/o banks) differential buffers with true lvds outputs (50% on left and right side) single-ended buffers with complementary outputs (all i/o banks) differential buffers with true lvds outputs (50% on left and right side) differential output emulation capability all i/o banks all i/o banks all i/o banks all i/o banks pci support no no top side only top side only vccio (typ.) input standard 3.3v 2.5v 1.8v 1.5v 1.2v single ended interfaces lvttl lvcmos33 lvcmos25 lvcmos18 lvcmos15 lvcmos12 pci 1 differential interfaces blvds 2 , lvds 2 , lvpecl 2 , rsds 2 1. top banks of la-machxo1200 and la-machxo2280 devices only. 2. la-machxo1200 and la-machxo2280 devices only.
2-18 architecture lattice semiconductor la-machxo automotive family data sheet table 2-10. supported output standards sysio buffer banks the number of banks vary between the devices of this family. eight banks surround the two larger devices, the la- machxo1200 and la-machxo2280 (two banks per side). the la-machxo640 has four banks (one bank per side). the smallest member of this family, the la-machxo256, has only two banks. each sysio buffer bank is capable of supporting multiple i/o standards. each bank has its own i/o supply voltage (v ccio ) which allows it to be completely independent from the other banks. figure 2-18, figure 2-18, figure 2-20 and figure 2-21 shows the sysio banks and their associated supplies for all devices. output standard drive v ccio (typ.) single-ended interfaces lvttl 4ma, 8ma, 12ma, 16ma 3.3 lvcmos33 4ma, 8ma, 12ma, 14ma 3.3 lvcmos25 4ma, 8ma, 12ma, 14ma 2.5 lvcmos18 4ma, 8ma, 12ma, 14ma 1.8 lvcmos15 4ma, 8ma 1.5 lvcmos12 2ma, 6ma 1.2 lvcmos33, open drain 4ma, 8ma, 12ma, 14ma lvcmos25, open drain 4ma, 8ma, 12ma, 14ma lvcmos18, open drain 4ma, 8ma, 12ma, 14ma lvcmos15, open drain 4ma, 8ma lvcmos12, open drain 2ma, 6ma pci33 3 n/a 3.3 differential interfaces lvds 1, 2 n/a 2.5 blvds, rsds 2 n/a 2.5 lvpecl 2 n/a 3.3 1. la-machxo1200 and la-machxo2280 devices have dedicated lvds buffers. 2. these interfaces can be emulated with external resistors in all devices. 3. top banks of la-machxo1200 and la-machxo2280 devices only.
2-19 architecture lattice semiconductor la-machxo automotive family data sheet figure 2-18. la-machxo2280 banks figure 2-19. la-machxo1200 banks gnd bank 2 v ccio2 gnd bank 3 v ccio3 gnd bank 7 v ccio7 gnd bank 6 v ccio6 gnd bank 5 v ccio5 gnd bank 4 v ccio4 gnd bank 1 v ccio1 v ccio0 1 34 1 33 1 34 33 1 136 131 135 gnd bank 0 135 gnd bank 2 v ccio2 gnd bank 3 v ccio3 gnd bank 7 v ccio7 gnd bank 6 v ccio6 gnd bank 5 v ccio5 gnd bank 4 v ccio4 gnd bank 1 v ccio1 v ccio0 1 26 1 28 1 26 28 1 130 120 129 gnd bank 0 124
2-20 architecture lattice semiconductor la-machxo automotive family data sheet figure 2-20. la-machxo640 banks figure 2-21. la-machxo256 banks hot socketing the la-machxo automotive devices have been carefully designed to ensure predictable behavior during power- up and power-down. leakage into i/o pins is controlled to within speci?d limits. this allows for easy integration gnd bank 1 v cco1 gnd bank 3 v cco3 gnd bank 2 v cco2 1 40 1 40 1 37 gnd bank 0 v cco 0 42 1 v bank 1 1 41 37 bank 0 1 gnd cco0 gnd cco1 v
2-21 architecture lattice semiconductor la-machxo automotive family data sheet with the rest of the system. these capabilities make the la-machxo ideal for many multiple power supply and hot-swap applications. sleep mode the la-machxo ? devices (v cc = 1.8/2.5/3.3v) have a sleep mode that allows standby current to be reduced dramatically during periods of system inactivity. entry and exit to sleep mode is controlled by the sleepn pin. during sleep mode, the logic is non-operational, registers and ebr contents are not maintained, and i/os are tri- stated. do not enter sleep mode during device programming or con?uration operation. in sleep mode, power sup- plies are in their normal operating range, eliminating the need for external switching of power supplies. table 2-11 compares the characteristics of normal, off and sleep modes. table 2-11. characteristics of normal, off and sleep modes sleepn pin characteristics the sleepn pin behaves as an lvcmos input with the voltage standard appropriate to the vcc supply for the device. this pin also has a weak pull-up, along with a schmidt trigger and glitch ?ter to prevent false triggering. an external pull-up to vcc is recommended when sleep mode is not used to ensure the device stays in normal oper- ation mode. typically, the device enters sleep mode several hundred nanoseconds after sleepn is held at a valid low and restarts normal operation as speci?d in the sleep mode timing table. the ac and dc speci?ations por- tion of this data sheet shows a detailed timing diagram. oscillator every la-machxo device has an internal cmos oscillator. the oscillator can be routed as an input clock to the clock tree or to general routing resources. the oscillator frequency can be divided by internal logic. there is a ded- icated programming bit to enable/disable the oscillator. the oscillator frequency ranges from 16mhz to 26mhz. con?uration and testing the following section describes the con?uration and testing features of the la-machxo automotive family of devices. ieee 1149.1-compliant boundary scan testability all la-machxo devices have boundary scan cells that are accessed through an ieee 1149.1 compliant test access port (tap). this allows functional testing of the circuit board, on which the device is mounted, through a serial scan path that can access all critical logic nodes. internal registers are linked internally, allowing test data to be shifted in and loaded directly onto test nodes, or test data to be captured and shifted out for veri?ation. the test access port consists of dedicated i/os: tdi, tdo, tck and tms. the test access port shares its power supply with one of the vccio banks (la-machxo256: v ccio1 ; la-machxo640: v ccio2 ; la-machxo1200 and la- machxo2280: v ccio5 ) and can operate with lvcmos3.3, 2.5, 1.8, 1.5, and 1.2 standards. for more details on boundary scan test, please see information regarding additional technical documentation at the end of this data sheet. characteristic normal off sleep sleepn pin high low static icc typical <10ma 0 typical <100ua i/o leakage <10? <1ma <10? power supplies vcc/vccio/vccaux normal range 0 normal range logic operation user de?ed non operational non operational i/o operation user de?ed tri-state tri-state jtag and programming circuitry operational non-operational non-operational ebr contents and registers maintained non-maintained non-maintained
2-22 architecture lattice semiconductor la-machxo automotive family data sheet device con?uration all la-machxo devices contain a test access port that can be used for device con?uration and programming. the non-volatile memory in the la-machxo can be con?ured in two different modes: in ieee 1532 mode via the ieee 1149.1 port. in this mode, the device is off-line and i/os are controlled by bscan registers. in background mode via the ieee 1149.1 port. this allows the device to remain operational in user mode while reprogramming takes place. the sram con?uration memory can be con?ured in three different ways: at power-up via the on-chip non-volatile memory. after a refresh command is issued via the ieee 1149.1 port. in ieee 1532 mode via the ieee 1149.1 port. figure 2-22 provides a pictorial representation of the different programming modes available in the la-machxo devices. on power-up, the sram is ready to be con?ured with ieee 1149.1 serial tap port using ieee 1532 pro- tocols. leave alone i/o when using ieee 1532 mode for non-volatile memory programming, sram con?uration, or issuing a refresh command, users may specify i/os as high, low, tristated or held at current value. this provides excellent ?xibility for implementing systems where recon?uration or reprogramming occurs on-the-?. transfr (t rans parent f ield r econ?uration) transfr (tfr) is a unique lattice technology that allows users to update their logic in the ?ld without interrupting system operation using a single ispvm command. see lattice technical note #tn1087, minimizing system inter- ruption during con?uration using transfr technology, for details. security the la-machxo automotive devices contain security bits that, when set, prevent the readback of the sram con- ?uration and non-volatile memory spaces. once set, the only way to clear the security bits is to erase the memory space. for more information on device con?uration, please see details of additional technical documentation at the end of this data sheet. aec-q100 tested and quali?d the automotive electronics council (aec) consists of two committees: the quality systems committee and the component technical committee. these committees are composed of representatives from sustaining and other associate members. the aec component technical committee is the standardization body for establishing stan- dards for reliable, high quality electronic components. in particular, the aec-q100 speci?ation ?tress test for quali?ation for integrated circuits de?es quali?ation and re-quali?ation requirements for electronic compo- nents. components meeting these speci?ations are suitable for use in the harsh automotive environment without additional component-level quali?ation testing. lattice's la-ispmach 4000v and la-machxo devices completed and passed the requirements of the aec-q100 speci?ation.
2-23 architecture lattice semiconductor la-machxo automotive family data sheet figure 2-22. la-machxo con?uration and programming density shifting the la-machxo family has been designed to enable density migration in the same package. furthermore, the architecture ensures a high success rate when performing design migration from lower density parts to higher den- sity parts. in many cases, it is also possible to shift a lower utilization design targeted for a high-density device to a lower density device. however, the exact details of the ?al resource utilization will impact the likely success in each case. isp 1149.1 tap port port mode program in seconds download in microseconds configure in milliseconds background 1532 non-volatile memory space sram memory space power-up refresh
november 2007 data sheet ds1003 ?2007 lattice semiconductor corp. all lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www .latticesemi.com/legal. all other brand or product names are trademarks or registered trademarks of their respective holders. the speci?ations and information herein are subject to change without notice. www.latticesemi.com 3-1 ds1003 dc and switching_01.3 recommended operating conditions 1 absolute maximum ratings 1, 2, 3 1. stress above those listed under the ?bsolute maximum ratings may cause permanent damage to the device. functional operation of the device at these or any other conditions above those indicated in the operational sections of this speci?ation is not implied. 2. compliance with the lattice thermal management document is required. 3. all voltages referenced to gnd. lcmxo e (1.2v) lcmxo c (1.8v/2.5v/3.3v) supply voltage v cc . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 1.32v . . . . . . . . . . . . . . . -0.5 to 3.75v supply voltage v ccaux . . . . . . . . . . . . . . . . . . . . . -0.5 to 3.75v . . . . . . . . . . . . . . . -0.5 to 3.75v output supply voltage v ccio . . . . . . . . . . . . . . . . -0.5 to 3.75v . . . . . . . . . . . . . . . -0.5 to 3.75v i/o tristate voltage applied 4 . . . . . . . . . . . . . . . . . -0.5 to 3.75v . . . . . . . . . . . . . . . -0.5 to 3.75v dedicated input voltage applied 4 . . . . . . . . . . . . . -0.5 to 3.75v . . . . . . . . . . . . . . . -0.5 to 4.25v storage temperature (ambient). . . . . . . . . . . . . . . -65 to 150? . . . . . . . . . . . . . . . -65 to 150? junction temp. (tj) . . . . . . . . . . . . . . . . . . . . . . . . . . +125? . . . . . . . . . . . . . . . . . . . +125? 4. overshoot and undershoot of -2v to (v ihmax + 2) volts is permitted for a duration of <20ns. symbol parameter min. max. units v cc core supply voltage for 1.2v devices 1.14 1.26 v core supply voltage for 1.8v/2.5v/3.3v devices 1.71 3.465 v v ccaux 3 auxiliary supply voltage 3.135 3.465 v v ccio 2 i/o driver supply voltage 1.14 3.465 v t jauto junction temperature automotive operation -40 125 o c t jflashauto junction temperature, flash programming, automotive -40 125 o c 1. like power supplies must be tied together. for example, if v ccio and v cc are both 2.5v, they must also be the same supply. 3.3v v ccio and 1.2v v ccio should be tied to v ccaux or 1.2v v cc respectively. 2. see recommended voltages by i/o standard in subsequent table. 3. v cc must reach minimum v cc value before v ccaux reaches 2.5v. la-machxo256 and la-machxo640 hot socketing speci?ations 1, 2, 3 1. insensitive to sequence of v cc, v ccaux, and v ccio . however, assumes monotonic rise/fall rates for v cc, v ccaux, and v ccio. 2. 0 v cc v cc (max), 0 v ccio v ccio (max) and 0 v ccaux v ccaux (max). 3. i dk is additive to i pu, i pd or i bh . symbol parameter condition min. typ. max units i dk input or i/o leakage current 0 v in v ih (max) +/-1000 ? la-machxo automotive family data sheet dc and switching characteristics
3-2 dc and switching characteristics lattice semiconductor la-machxo automotive family data sheet dc electrical characteristics over recommended operating conditions la-machxo1200 and la-machxo2280 hot socketing speci?ations 1, 2, 3, 4 1. insensitive to sequence of v cc, v ccaux, and v ccio . however, assumes monotonic rise/fall rates for v cc, v ccaux, and v ccio. 2. 0 v cc v cc (max), 0 v ccio v ccio (max), and 0 v ccaux v ccaux (max). 3. i dk is additive to i pu, i pw or i bh . 4. lvcmos and lvttl only. symbol parameter condition min. typ. max. units non-lvds general purpose sysios i dk input or i/o leakage current 0 v in v ih (max.) +/-1000 ? lvds general purpose sysios i dk_lvds input or i/o leakage current v in v ccio +/-1000 ? v in > v ccio ?5ma symbol parameter condition min. typ. max. units i il, i ih 1, 4, 5 input or i/o leakage 0 v in (v ccio - 0.2v) 10 ? (v ccio - 0.2v) < v in 3.6v 40 ? i pu i/o active pull-up current 0 v in 0.7 v ccio -30 -150 ? i pd i/o active pull-down current v il (max) v in v ih (max) 30 150 ? i bhls bus hold low sustaining current v in = v il (max) 30 ? i bhhs bus hold high sustaining current v in = 0.7v ccio -30 ? i bhlo bus hold low overdrive current 0 v in v ih (max) 150 ? i bhho bus hold high overdrive current 0 v in v ih (max) -150 ? v bht 3 bus hold trip points 0 v in v ih (max) v il (max) v ih (min) v c1 i/o capacitance 2 v ccio = 3.3v, 2.5v, 1.8v, 1.5v, 1.2v, v cc = typ., v io = 0 to v ih (max) ?pf c2 dedicated input capacitance 2 v ccio = 3.3v, 2.5v, 1.8v, 1.5v, 1.2v, v cc = typ., v io = 0 to v ih (max) ?pf 1. input or i/o leakage current is measured with the pin con?ured as an input or as an i/o with the output driver tri-stated. i t is not measured with the output driver active. bus maintenance circuits are disabled. 2. t a 25?, f = 1.0mhz 3. please refer to v il and v ih in the sysio single-ended dc electrical characteristics table of this document. 4. not applicable to sleepn pin. 5. when v ih is higher than v ccio , a transient current typically of 30ns in duration or less with a peak current of 6ma can occur on the high-to- low transition. for la-machxo1200 and la-machxo2280 true lvds output pins, v ih must be less than or equal to v ccio .
3-3 dc and switching characteristics lattice semiconductor la-machxo automotive family data sheet supply current (sleep mode) 1, 2 symbol parameter device typ. 3 max. units i cc core power supply lcmxo256c 12 25 ? lcmxo640c 12 25 ? i ccaux auxiliary power supply lcmxo256c 1 15 a lcmxo640c 1 25 a i ccio bank power supply 4 all lcmxo ? devices 2 30 a 1. assumes all inputs are con?ured as lvcmos and held at the vccio or gnd. 2. frequency = 0mhz. 3. t a = 25?, power supplies at nominal voltage. 4. per bank. supply current (standby) 1, 2, 3, 4 over recommended operating conditions 1. for further information on supply current, please see details of additional technical documentation at the end of this data s heet. 2. assumes all outputs are tristated, all inputs are con?ured as lvcmos and held at v ccio or gnd. 3. frequency = 0mhz. 4. user pattern = blank. symbol parameter device typ. 5 5. t j = 25 o c, power supplies at nominal voltage. units i cc core power supply lcmxo256c 7 ma lcmxo640c 9 ma lcmxo256e 4 ma lcmxo640e 6 ma lcmxo1200e 10 ma lcmxo2280e 12 ma i ccaux auxiliary power supply v ccaux = 3.3v lcmxo256e/c 5 ma lcmxo640e/c 7 ma lcmxo1200e 12 ma lcmxo2280e 13 ma i ccio bank power supply 6 6. per bank. v ccio = 2.5v. does not include pull-up/pull-down. all devices 2 ma
3-4 dc and switching characteristics lattice semiconductor la-machxo automotive family data sheet initialization supply current 1, 2, 3, 4 over recommended operating conditions 1. for further information on supply current, please see details of additional technical documentation at the end of this data s heet. 2. assumes all i/o pins are held at v ccio or gnd. 3. frequency = 0mhz. 4. typical user pattern. symbol parameter device typ. 5 5. t j = 25 o c, power supplies at nominal voltage. units i cc core power supply lcmxo256c 13 ma lcmxo640c 17 ma lcmxo256e 10 ma lcmxo640e 14 ma lcmxo1200e 18 ma lcmxo2280e 20 ma i ccaux auxiliary power supply v ccaux = 3.3v lcmxo256e/c 10 ma lcmxo640e/c 13 ma lcmxo1200e 24 ma lcmxo2280e 25 ma i ccio bank power supply 6 6. per bank, v ccio = 2.5v. does not include pull-up/pull-down. all devices 2 ma
3-5 dc and switching characteristics lattice semiconductor la-machxo automotive family data sheet programming and erase flash supply current 1, 2, 3, 4 symbol parameter device typ. 5 units i cc core power supply lcmxo256c 9 ma lcmxo640c 11 ma lcmxo256e 6 ma lcmxo640e 8 ma lcmxo1200e 12 ma lcmxo2280e 14 ma i ccaux auxiliary power supply v ccaux = 3.3v lcmxo256e/c 8 ma lcmxo640e/c 10 ma lcmxo1200e 15 ma lcmxo2280e 16 ma i ccio bank power supply 6 all devices 2 ma 1. for further information on supply current, please see details of additional technical documentation at the end of this data s heet. 2. assumes all i/o pins are held at v ccio or gnd. 3. typical user pattern. 4. jtag programming is at 25mhz. 5. t j = 25?, power supplies at nominal voltage. 6. per bank. v ccio = 2.5v. does not include pull-up/pull-down.
3-6 dc and switching characteristics lattice semiconductor la-machxo automotive family data sheet sysio recommended operating conditions standard v ccio (v) min. typ. max. lvcmos 3.3 3.135 3.3 3.465 lvcmos 2.5 2.375 2.5 2.625 lvcmos 1.8 1.71 1.8 1.89 lvcmos 1.5 1.425 1.5 1.575 lvcmos 1.2 1.14 1.2 1.26 lvttl 3.135 3.3 3.465 pci 3 3.135 3.3 3.465 lvds 1, 2 2.375 2.5 2.625 lvpecl 1 3.135 3.3 3.465 blvds 1 2.375 2.5 2.625 rsds 1 2.375 2.5 2.625 1. inputs on chip. outputs are implemented with the addition of external resistors. 2. machxo1200 and machxo2280 devices have dedicated lvds buffers 3. input on the top bank of the machxo1200 and machxo2280 only.
3-7 dc and switching characteristics lattice semiconductor la-machxo automotive family data sheet sysio single-ended dc electrical characteristics input/output standard v il v ih v ol max. (v) v oh min. (v) i ol 1 (ma) i oh 1 (ma) min. (v) max. (v) min. (v) max. (v) lvcmos 3.3 -0.3 0.8 2.0 3.6 0.4 v ccio - 0.4 16, 12, 8, 4 -14, -12, -8, -4 0.2 v ccio - 0.2 0.1 -0.1 lvttl -0.3 0.8 2.0 3.6 0.4 2.4 16 -16 0.4 v ccio - 0.4 12, 8, 4 -12, -8, -4 0.2 v ccio - 0.2 0.1 -0.1 lvcmos 2.5 -0.3 0.7 1.7 3.6 0.4 v ccio - 0.4 16, 12, 8, 4 -14, -12, -8, -4 0.2 v ccio - 0.2 0.1 -0.1 lvcmos 1.8 -0.3 0.35v ccio 0.65v ccio 3.6 0.4 v ccio - 0.4 16, 12, 8, 4 -14, -12, -8, -4 0.2 v ccio - 0.2 0.1 -0.1 lvcmos 1.5 -0.3 0.35v ccio 0.65v ccio 3.6 0.4 v ccio - 0.4 8, 4 -8, -4 0.2 v ccio - 0.2 0.1 -0.1 lvcmos 1.2 (? version) -0.3 0.42 0.78 3.6 0.4 v ccio - 0.4 6, 2 -6, -2 0.2 v ccio - 0.2 0.1 -0.1 lvcmos 1.2 (? version) -0.3 0.35v cc 0.65v cc 3.6 0.4 v ccio - 0.4 6, 2 -6, -2 0.2 v ccio - 0.2 0.1 -0.1 pci -0.3 0.3v ccio 0.5v ccio 3.6 0.1v ccio 0.9v ccio 1.5 -0.5 1. the average dc current drawn by i/os between gnd connections, or between the last gnd in an i/o bank and the end of an i/o ba nk, as shown in the logic signal connections table shall not exceed n * 8ma. where n is the number of i/os between bank gnd connection s or between the last gnd in a bank and the end of a bank.
3-8 dc and switching characteristics lattice semiconductor la-machxo automotive family data sheet sysio differential electrical characteristics lvds over recommended operating conditions lvds emulation la-machxo automotive devices can support lvds outputs via emulation (lvds25e), in addition to the lvds sup- port that is available on-chip on certain devices. the output is emulated using complementary lvcmos outputs in conjunction with resistors across the driver outputs on all devices. the scheme shown in figure 3-1 is one possible solution for lvds standard implementation. resistor values in figure 3-1 are industry standard values for 1% resis- tors. figure 3-1. lvds using external resistors (lvds25e) the lvds differential input buffers are available on certain devices in the la-machxo family. parameter symbol parameter description test conditions min. typ. max. units v inp, v inm input voltage 0 2.4 v v thd differential input threshold +/-100 mv v cm input common mode voltage 100mv v thd v thd /2 1.2 1.8 v 200mv v thd v thd /2 1.2 1.9 v 350mv v thd v thd /2 1.2 2.0 v i in input current power on +/-10 ? v oh output high voltage for v op or v om r t = 100 ohm 1.38 1.60 v v ol output low voltage for v op or v om r t = 100 ohm 0.9v 1.03 v v od output voltage differential (v op - v om ), r t = 100 ohm 250 350 450 mv v od change in v od between high and low 50 mv v os output voltage offset (v op - v om )/2, r t = 100 ohm 1.125 1.25 1.375 v v os change in v os between h and l 50 mv i osd output short circuit current v od = 0v driver outputs shorted 6ma 15 8 15 8 zo = 100 140 100 on-chip on-chip off-chip off-chip v ccio = 2.5 8 ma 8 ma n ote: all resistors are ? % . v ccio = 2.5 + - em u lated l v ds b u ffer
3-9 dc and switching characteristics lattice semiconductor la-machxo automotive family data sheet table 3-1. lvds dc conditions over recommended operating conditions blvds the la-machxo automotive family supports the blvds standard through emulation. the output is emulated using complementary lvcmos outputs in conjunction with a parallel external resistor across the driver outputs. the input standard is supported by the lvds differential input buffer on certain devices. blvds is intended for use when multi-drop and bi-directional multi-point differential signaling is required. the scheme shown in figure 3-2 is one possible solution for bi-directional multi-point differential signals. figure 3-2. blvds multi-point output example parameter description typical units z out output impedance 20 r s driver series resistor 294 r p driver parallel resistor 121 r t receiver termination 100 v oh output high voltage 1.43 v v ol output low voltage 1.07 v v od output differential voltage 0.35 v v cm output common mode voltage 1.25 v z back back impedance 100 i dc dc output current 3.66 ma heavily loaded backplane, effective zo ~ 45 to 90 ohms differential 2.5v 80 80 80 80 80 80 45-90 ohms 45-90 ohms 80 2.5v 2.5v 2.5v 2.5v 2.5v 2.5v 2.5v + - . . . + - . . . + - + - 16ma 16ma 16ma 16ma 16ma 16ma 16ma 16ma
3-10 dc and switching characteristics lattice semiconductor la-machxo automotive family data sheet table 3-2. blvds dc conditions 1 over recommended operating conditions lvpecl the la-machxo automotive family supports the differential lvpecl standard through emulation. this output stan- dard is emulated using complementary lvcmos outputs in conjunction with a parallel resistor across the driver outputs on all the devices. the lvpecl input standard is supported by the lvds differential input buffer on certain devices. the scheme shown in figure 3-3 is one possible solution for point-to-point signals. figure 3-3. differential lvpecl table 3-3. lvpecl dc conditions 1 over recommended operating conditions nominal symbol description zo = 45 zo = 90 units z out output impedance 100 100 ohm r tleft left end termination 45 90 ohm r tright right end termination 45 90 ohm v oh output high voltage 1.375 1.48 v v ol output low voltage 1.125 1.02 v v od output differential voltage 0.25 0.46 v v cm output common mode voltage 1.25 1.25 v i dc dc output current 11.2 10.2 ma 1. for input buffer, see lvds table. symbol description nominal units z out output impedance 100 ohm r p driver parallel resistor 150 ohm r t receiver termination 100 ohm v oh output high voltage 2.03 v v ol output low voltage 1.27 v v od output differential voltage 0.76 v v cm output common mode voltage 1.65 v z back back impedance 85.7 ohm i dc dc output current 12.7 ma 1. for input buffer, see lvds table. transmission line, zo = 100 ohm differential 100 ohms 100 ohms 16ma 16ma 100 ohms off-chip on-chip v ccio = 3.3v v ccio = 3.3v + - 150 ohms on-chip off-chip
3-11 dc and switching characteristics lattice semiconductor la-machxo automotive family data sheet for further information on lvpecl, blvds and other differential interfaces please see details of additional techni- cal documentation at the end of the data sheet. rsds the la-machxo automotive family supports the differential rsds standard. the output standard is emulated using complementary lvcmos outputs in conjunction with a parallel resistor across the driver outputs on all the devices. the rsds input standard is supported by the lvds differential input buffer on certain devices. the scheme shown in figure 3-4 is one possible solution for rsds standard implementation. use lvds25e mode with suggested resistors for rsds operation. resistor values in figure 3-4 are industry standard values for 1% resis- tors. figure 3-4. rsds (reduced swing differential standard) table 3-4. rsds dc conditions parameter description typical units z out output impedance 20 ohm r s driver series resistor 294 ohm r p driver parallel resistor 121 ohm r t receiver termination 100 ohm v oh output high voltage 1.35 v v ol output low voltage 1.15 v v od output differential voltage 0.20 v v cm output common mode voltage 1.25 v z back back impedance 101.5 ohm i dc dc output current 3.66 ma 100 294 294 on-chip on-chip off-chip emulated rsds buffer vccio = 2.5v vccio = 2.5v 8ma 8ma zo = 100 + - 121 off-chip
3-12 dc and switching characteristics lattice semiconductor la-machxo automotive family data sheet typical building block function performance 1 pin-to-pin performance (lvcmos25 12ma drive) register-to-register performance derating logic timing logic timing provided in the following sections of the data sheet and the isplever design tools are worst case numbers in the operating range. actual delays may be much faster. the isplever design tool from lattice can pro- vide logic timing numbers at a particular temperature and voltage. function -3 timing units basic functions 16-bit decoder 9.4 ns 4:1 mux 6.3 ns 16:1 mux 7.1 ns function -3 timing units basic functions 16:1 mux 348 mhz 16-bit adder 209 mhz 16-bit counter 277 mhz 64-bit counter 143 mhz embedded memory functions (1200 and 2280 devices only) 256x36 single port ram 203 mhz 512x18 true-dual port ram 203 mhz distributed memory functions 16x2 single port ram 310 mhz 64x2 single port ram 229 mhz 128x4 single port ram 186 mhz 32x2 pseudo-dual port ram 224 mhz 64x4 pseudo-dual port ram 194 mhz 1. the above timing numbers are generated using the isplever design tool. exact performance may vary with device and tool version. the tool uses internal parameters that have been characterized but are not tested on every device. rev. a 0.19
3-13 dc and switching characteristics lattice semiconductor la-machxo automotive family data sheet la-machxo external switching characteristics 1 over recommended operating conditions parameter description device -3 units min. max. general i/o pin parameters (using global clock without pll) 1 t pd best case t pd through 1 lut lcmxo256 4.9 ns lcmxo640 4.9 ns lcmxo1200 5.1 ns lcmxo2280 5.1 ns t co best case clock to output - from pfu lcmxo256 5.6 ns lcmxo640 5.7 ns lcmxo1200 6.1 ns lcmxo2280 6.1 ns t su clock to data setup - to pfu lcmxo256 1.8 ns lcmxo640 1.5 ns lcmxo1200 1.6 ns lcmxo2280 1.5 ns t h clock to data hold - to pfu lcmxo256 -0.3 ns lcmxo640 -0.1 ns lcmxo1200 0.0 ns lcmxo2280 -0.4 ns f max_io clock frequency of i/o and pfu register lcmxo256 500 mhz lcmxo640 500 mhz lcmxo1200 500 mhz lcmxo2280 500 mhz t skew_pri global clock skew across device lcmxo256 240 ps lcmxo640 240 ps lcmxo1200 260 ps lcmxo2280 260 ps 1. general timing numbers based on lvcmos2.5v, 12 ma. rev. a 0.19
3-14 dc and switching characteristics lattice semiconductor la-machxo automotive family data sheet la-machxo internal timing parameters 1 over recommended operating conditions parameter description -3 units min. max. pfu/pff logic mode timing t lut4_pfu lut4 delay (a to d inputs to f output) 0.39 ns t lut6_pfu lut6 delay (a to d inputs to ofx output) 0.62 ns t lsr_pfu set/reset to output of pfu 1.26 ns t sum_pfu clock to mux (m0,m1) input setup time 0.15 ns t hm_pfu clock to mux (m0,m1) input hold time -0.07 ns t sud_pfu clock to d input setup time 0.18 ns t hd_pfu clock to d input hold time -0.04 ns t ck2q_pfu clock to q delay, d-type register con?uration 0.56 ns t le2q_pfu clock to q delay latch con?uration 0.74 ns t ld2q_pfu d to q throughput delay when latch is enabled 0.77 ns pfu dual port memory mode timing t coram_pfu clock to output 0.56 ns t sudata_pfu data setup time -0.25 ns t hdata_pfu data hold time 0.39 ns t suaddr_pfu address setup time -0.65 ns t haddr_pfu address hold time 0.99 ns t suwren_pfu write/read enable setup time -0.30 ns t hwren_pfu write/read enable hold time 0.47 ns pio input/output buffer timing t in_pio input buffer delay 1.06 ns t out_pio output buffer delay 1.80 ns ebr timing (1200 and 2280 devices only) t co_ebr clock to output from address or data with no output register 3.14 ns t coo_ebr clock to output from ebr output register 0.75 ns t sudata_ebr setup data to ebr memory -0.37 ns t hdata_ebr hold data to ebr memory 0.57 ns t suaddr_ebr setup address to ebr memory -0.37 ns t haddr_ebr hold address to ebr memory 0.57 ns t suwren_ebr setup write/read enable to ebr memory -0.23 ns t hwren_ebr hold write/read enable to ebr memory 0.36 ns t suce_ebr clock enable setup time to ebr output register 0.27 ns t hce_ebr clock enable hold time to ebr output register -0.18 ns t rsto_ebr reset to output delay time from ebr output regis- ter 1.44 ns pll parameters (1200 and 2280 devices only) t rstrec reset recovery to rising clock 1.00 ns t rstsu reset signal setup time 1.00 ns 1. internal parameters are characterized but not tested on every device. rev. a 0.19
3-15 dc and switching characteristics lattice semiconductor la-machxo automotive family data sheet la-machxo family timing adders 1, 2, 3 over recommended operating conditions buffer type description -3 units input adjusters lvds25 4 lvds 0.61 ns blvds25 4 blvds 0.61 ns lvpecl33 4 lvpecl 0.59 ns lvttl33 lvttl 0.01 ns lvcmos33 lvcmos 3.3 0.01 ns lvcmos25 lvcmos 2.5 0.00 ns lvcmos18 lvcmos 1.8 0.10 ns lvcmos15 lvcmos 1.5 0.19 ns lvcmos12 lvcmos 1.2 0.56 ns pci33 4 pci 0.01 ns output adjusters lvds25e lvds 2.5 e -0.18 ns lvds25 4 lvds 2.5 -0.30 ns blvds25 blvds 2.5 -0.04 ns lvpecl33 lvpecl 3.3 0.05 ns lvttl33_4ma lvttl 4ma drive 0.05 ns lvttl33_8ma lvttl 8ma drive 0.08 ns lvttl33_12ma lvttl 12ma drive -0.01 ns lvttl33_16ma lvttl 16ma drive 0.70 ns lvcmos33_4ma lvcmos 3.3 4ma drive 0.05 ns lvcmos33_8ma lvcmos 3.3 8ma drive 0.08 ns lvcmos33_12ma lvcmos 3.3 12ma drive -0.01 ns lvcmos33_14ma lvcmos 3.3 14ma drive 0.70 ns lvcmos25_4ma lvcmos 2.5 4ma drive 0.07 ns lvcmos25_8ma lvcmos 2.5 8ma drive 0.13 ns lvcmos25_12ma lvcmos 2.5 12ma drive 0.00 ns lvcmos25_14ma lvcmos 2.5 14ma drive 0.47 ns lvcmos18_4ma lvcmos 1.8 4ma drive 0.15 ns lvcmos18_8ma lvcmos 1.8 8ma drive 0.06 ns lvcmos18_12ma lvcmos 1.8 12ma drive -0.08 ns lvcmos18_14ma lvcmos 1.8 14ma drive 0.09 ns lvcmos15_4ma lvcmos 1.5 4ma drive 0.22 ns lvcmos15_8ma lvcmos 1.5 8ma drive 0.07 ns lvcmos12_2ma lvcmos 1.2 2ma drive 0.36 ns lvcmos12_6ma lvcmos 1.2 6ma drive 0.07 ns pci33 4 pci33 2.59 ns 1. timing adders are characterized but not tested on every device. 2. lvcmos timing is measured with the load speci?d in switching test conditions table. 3. all other standards tested according to the appropriate speci?ations. 4. i/o standard only available in lcmxo1200 and lcmxo2280 devices. rev. a 0.19
3-16 dc and switching characteristics lattice semiconductor la-machxo automotive family data sheet sysclock pll timing over recommended operating conditions la-machxo ? sleep mode timing parameter descriptions conditions min. max. units f in input clock frequency (clki, clkfb) 25 420 mhz f out output clock frequency (clkop, clkos) 25 420 mhz f out2 k-divider output frequency (clkok) 0.195 210 mhz f vco pll vco frequency 420 840 mhz f pfd phase detector input frequency 25 mhz ac characteristics t dt output clock duty cycle default duty cycle selected 3 45 55 % t ph 4 output phase accuracy 0.05 ui t opjit 1 output clock period jitter fout 100mhz +/-120 ps fout < 100mhz 0.02 uipp t sk input clock to output clock skew divider ratio = integer +/-200 ps t w output clock pulse width at 90% or 10% 3 1ns t lock 2 pll lock-in time 150 ? t pa programmable delay unit 100 450 ps t ipjit input clock period jitter +/-200 ps t fbkdly external feedback delay 10 ns t hi input clock high time 90% to 90% 0.5 ns t lo input clock low time 10% to 10% 0.5 ns t rst rst pulse width 10 ns 1. jitter sample is taken over 10,000 samples of the primary pll output with a clean reference clock. 2. output clock is valid after t lock for pll reset and dynamic delay adjustment. 3. using lvds output buffers. 4. clkos as compared to clkop output. rev. a 0.19 symbol parameter device min. typ. max units t pwrdn sleepn low to power down all 400 ns t pwrup sleepn high to power up lcmxo256 400 ? lcmxo640 600 ? t wsleepn sleepn pulse width all 400 ns t wawake sleepn pulse rejection all 100 ns rev. a 0.19 sleepn t pwrup power down mode t pwrdn t wsleepn or t wawake i/o
3-17 dc and switching characteristics lattice semiconductor la-machxo automotive family data sheet flash download time jtag port timing speci?ations over recommended operating conditions figure 3-5. jtag port timing waveforms symbol parameter min. typ. max. units t refresh minimum v cc or v ccaux (later of the two supplies) to device i/o active lcmxo256 0.4 ms lcmxo640 0.6 ms lcmxo1200 0.8 ms lcmxo2280 1.0 ms symbol parameter min. max. units f max tck [bscan] clock frequency 25 mhz t btcp tck [bscan] clock pulse width 40 ns t btcph tck [bscan] clock pulse width high 20 ns t btcpl tck [bscan] clock pulse width low 20 ns t bts tck [bscan] setup time 8 ns t bth tck [bscan] hold time 10 ns t btrf tck [bscan] rise/fall time 50 mv/ns t btco tap controller falling edge of clock to output valid 10 ns t btcodis tap controller falling edge of clock to output disabled 10 ns t btcoen tap controller falling edge of clock to output enabled 10 ns t btcrs bscan test capture register setup time 8 ns t btcrh bscan test capture register hold time 25 ns t butco bscan test update register, falling edge of clock to output valid 25 ns t btuodis bscan test update register, falling edge of clock to output disabled 25 ns t btupoen bscan test update register, falling edge of clock to output enabled 25 ns rev. a 0.19 tms tdi tck tdo data to b e capt u red from i/o data to b e dri v en o u t to i/o a t a d d i l a v a t a d d i l a v a t a d d i l a v a t a d d i l a v data capt u red t btcph t btcpl t btcoe n t btcrs t btupoe n t butco t btuodis t btcrh t btco t btcodis t bts t bth t btcp
3-18 dc and switching characteristics lattice semiconductor la-machxo automotive family data sheet switching test conditions figure 3-6 shows the output test load that is used for ac testing. the speci? values for resistance, capacitance, voltage, and other test conditions are shown in figure 3-5. figure 3-6. output test load, lvttl and lvcmos standards table 3-5. test fixture required components, non-terminated interfaces test condition r 1 c l timing ref. v t lvttl and lvcmos settings (l -> h, h -> l) 0pf lvttl, lvcmos 3.3 = 1.5v lvcmos 2.5 = v ccio /2 lvcmos 1.8 = v ccio /2 lvcmos 1.5 = v ccio /2 lvcmos 1.2 = v ccio /2 lvttl and lvcmos 3.3 (z -> h) 188 0pf 1.5 v ol lvttl and lvcmos 3.3 (z -> l) v oh other lvcmos (z -> h) v ccio /2 v ol other lvcmos (z -> l) v ccio /2 v oh lvttl + lvcmos (h -> z) v oh - 0.15 v ol lvttl + lvcmos (l -> z) v ol - 0.15 v oh note: output test conditions for all other interfaces are determined by the respective standards. dut v t r1 cl test poi nt
november 2007 data sheet ds1003 ?2007 lattice semiconductor corp. all lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www .latticesemi.com/legal. all other brand or product names are trademarks or registered trademarks of their respective holders. the speci?ations and information herein are subject to change without notice. www.latticesemi.com 4-1 ds1003 pinouts_01.3 signal descriptions signal name i/o descriptions general purpose p[edge] [row/column number]_[a/b/c/d/e/f] i/o [edge] indicates the edge of the device on which the pad is located. valid edge designa- tions are l (left), b (bottom), r (right), t (top). [row/column number] indicates the pfu row or the column of the device on which the pio group exists. when edge is t (top) or (bottom), only need to specify row number. when edge is l (left) or r (right), only need to specify column number. [a/b/c/d/e/f] indicates the pio within the group to which the pad is connected. some of these user programmable pins are shared with special function pins. when not used as special function pins, these pins can be programmed as i/os for user logic. during con?uration of the user-programmable i/os, the user has an option to tri-state the i/os and enable an internal pull-up resistor. this option also applies to unused pins (or those not bonded to a package pin). the default during con?uration is for user-program- mable i/os to be tri-stated with an internal pull-up resistor enabled. gsrn i global reset signal (active low). dedicated pad, when not in use it can be used as an i/o pin. tsall i tsall is a dedicated pad for the global output enable signal. when tsall is high all the outputs are tristated. it is a dual function pin. when not in use, it can be used as an i/o pin. nc no connect. gnd gnd - ground. dedicated pins. v cc vcc - the power supply pins for core logic. dedicated pins. v ccaux vccaux - the auxiliary power supply pin. this pin powers up a variety of internal circuits including all the differential and referenced input buffers. dedicated pins. v cciox ? ccio - the power supply pins for i/o bank x. dedicated pins. sleepn 1 i sleep mode pin - active low sleep pin. when this pin is held high, the device operates nor- mally. this pin has a weak internal pull-up, but when unused, an external pull-up to v cc is recommended. when driven low, the device moves into sleep mode after a speci?d time. pll and clock functions (used as user programmable i/o pins when not used for pll or clock pins) [loc][0]_pll[t, c]_in reference clock (pll) input pads: [loc] indicates location. valid designations are ulm (upper pll) and llm (lower pll). t = true and c = complement. [loc][0]_pll[t, c]_fb optional feedback (pll) input pads: [loc] indicates location. valid designations are ulm (upper pll) and llm (lower pll). t = true and c = complement. pclk [n]_[1:0] primary clock pads, n per side. test and programming (dedicated pins) tms i test mode select input pin, used to control the 1149.1 state machine. tck i test clock input pin, used to clock the 1149.1 state machine. tdi i test data input pin, used to load data into the device using an 1149.1 state machine. tdo o output pin -test data output pin used to shift data out of the device using 1149.1. 1. applies to la-machxo ? devices only. nc for ? devices. la-machxo automotive family data sheet pinout information
4-2 pinout information lattice semiconductor la-machxo automotive family data sheet pin information summary pin type lamxo256c/e lamxo640c/e 100 tqfp 100 tqfp 144 tqfp 256 ftbga single ended user i/o 78 74 113 159 differential pair user i/o 1 38 17 43 79 muxed 6666 tap 4444 dedicated (total without supplies) 5555 vcc 2244 vccaux 1122 vccio bank0 3224 bank1 3224 bank2 2 2 4 bank3 2 2 4 gnd 8 101218 nc 0 0 0 52 single ended/differential i/o per bank bank0 41/20 18/5 29/10 42/21 bank1 37/18 21/4 30/11 40/20 bank2 14/2 24/9 36/18 bank3 21/6 30/13 40/20 1. these devices support emulated lvds outputs. lvds inputs are not supported. pin type lamxo1200e lamxo2280e 100 tqfp 144 tqfp 256 ftbga 100 tqfp 144 tqfp 256 ftbga 324 ftbga single ended user i/o 73 113 211 73 113 211 271 differential pair user i/o 1 27 48 105 30 47 105 134 muxed 6666666 tap 4444444 dedicated (total without supplies) 5555555 vcc 4442446 vccaux 2222222 vccio bank0 1121122 bank1 1121122 bank2 1121122 bank3 1121122 bank4 1121122 bank5 1121122 bank6 1121122 bank7 1121122 gnd 8 1218 8 121824 nc 0000000 single ended/differential i/o per bank bank0 10/3 14/6 26/13 9/3 13/6 24/12 34/17 bank1 8/2 15/7 28/14 9/3 16/7 30/15 36/18 bank2 10/4 15/7 26/13 10/4 15/7 26/13 34/17 bank3 11/5 15/7 28/14 11/5 15/7 28/14 34/17 bank4 8/3 14/5 27/13 8/3 14/4 29/14 35/17 bank5 5/2 10/4 22/11 5/2 10/4 20/10 30/15 bank6 10/3 15/6 28/14 10/4 15/6 28/14 34/17 bank7 11/5 15/6 26/13 11/5 15/6 26/13 34/17 1. these devices support on-chip lvds buffers for left and right i/o banks.
4-3 pinout information lattice semiconductor la-machxo automotive family data sheet power supply and nc signal 100 tqfp 1 144 tqfp 1 vcc lamxo256/640 : 35, 90 lamxo1200/2280 : 17, 35, 66, 91 21, 52, 93, 129 vccio0 lamxo256 : 60, 74, 92 lamxo640 : 80, 92 lamxo1200/2280 : 94 lamxo640 : 117, 135 lamxo1200/2280 : 135 vccio1 lamxo256 : 10, 24, 41 lamxo640 : 60, 74 lamxo1200/2280 : 80 lamxo640 : 82, 98 lamxo1200/2280 : 117 vccio2 lamxo256 : none lamxo640 : 29, 41 lamxo1200/2280 : 70 lamxo640 : 38, 63 lamxo1200/2280 : 98 vccio3 lamxo256 : none lamxo640 : 10, 24 lamxo1200/2280 : 56 lamxo640 : 10, 26 lamxo1200/2280 : 82 vccio4 lamxo256/640 : none lamxo1200/2280 : 44 lamxo640 : none lamxo1200/2280 : 63 vccio5 lamxo256/640 : none lamxo1200/2280 : 27 lamxo640 : none lamxo1200/2280 : 38 vccio6 lamxo256/640 : none lamxo1200/2280 : 20 lamxo640 : none lamxo1200/2280 : 26 vccio7 lamxo256/640 : none lamxo1200/2280 : 6 lamxo640 : none lamxo1200/2280 : 10 vccaux lamxo256/640 : 88 lamxo1200/2280 : 36, 90 53, 128 gnd 2 lamxo256 : 40, 84, 62, 75, 93, 12, 25, 42 lamxo640 : 40, 84, 81, 93, 62, 75, 30, 42, 12, 25 lamxo1200/2280 : 9, 41, 59, 83, 100, 76, 50, 26 16, 59, 88, 123, 118, 136, 83, 99, 37, 64, 11, 27 nc 3 1. pin orientation follows the conventional order from pin 1 marking of the top side view and counter-clockwise. 2. all grounds must be electrically connected at the board level. for fpbga and ftbga packages, the total number of gnd balls is less than the actual number of gnd logic connections from the die to the common package gnd plane. 3. nc pins should not be connected to any active signals, vcc or gnd.
4-4 pinout information lattice semiconductor la-machxo automotive family data sheet power supply and nc (cont.) signal 256 ftbga 1 324 ftbga 1 vcc g7, g10, k7, k10 f14, g11, g9, h7, l7, m9 vccio0 lamxo640 : f8, f7, f9, f10 lamxo1200/2280 : f8, f7 g8, g7 vccio1 lamxo640 : h11, g11, k11, j11 lamxo1200/2280 : f9, f10 g12, g10 vccio2 lamxo640 : l9, l10, l8, l7 lamxo1200/2280 : h11, g11 j12, h12 vccio3 lamxo640 : k6, j6, h6, g6 lamxo1200/2280 : k11, j11 l12, k12 vccio4 lamxo640 : none lamxo1200/2280 : l9, l10 m12, m11 vccio5 lamxo640 : none lamxo1200/2280 : l8, l7 m8, r9 vccio6 lamxo640 : none lamxo1200/2280 : k6, j6 m7, k7 vccio7 lamxo640 : none lamxo1200/2280 : h6, g6 h6, j7 vccaux t9, a8 m10, f9 gnd 2 a1, a16, f11, g8, g9, h7, h8, h9, h10, j7, j8, j9, j10, k8, k9, l6, t1, t16 e14, f16, h10, h11, h8, h9, j10, j11, j4, j8, j9, k10, k11, k17, k8, k9, l10, l11, l8, l9, n2, p14, p5, r7 nc 3 lamxo640 : e4, e5, f5, f6, c3, c2, g4, g5, h4, h5, k5, k4, m5, m4, p2, p3, n5, n6, m7, m8, n10, n11, r15, r16, p15, p16, m11, l11, n12, n13, m13, m12, k12, j12, f12, f13, e12, e13, d13, d14, b15, a15, c14, b14, e11, e10, e7, e6, d4, d3, b3, b2 lamxo1200 : none lamxo2280 : none 1. pin orientation a1 starts from the upper left corner of the top side view with alphabetical order ascending vertically and nu merical order ascending horizontally. 2. all grounds must be electrically connected at the board level. for fpbga and ftbga packages, the total number of gnd balls is less than the actual number of gnd logic connections from the die to the common package gnd plane. 3. nc pins should not be connected to any active signals, vcc or gnd.
4-5 pinout information lattice semiconductor la-machxo automotive family data sheet la-machxo256 and la-machxo640 logic signal connections: 100 tqfp pin number lamxo256 lamxo640 ball function bank dual function differential ball function bank dual function differential 1 pl2a 1 t pl2a 3 t 2 pl2b 1 c pl2c 3 t 3 pl3a 1 t pl2b 3 c 4 pl3b 1 c pl2d 3 c 5 pl3c 1 t pl3a 3 t 6 pl3d 1 c pl3b 3 c 7 pl4a 1 t pl3c 3 t 8 pl4b 1 c pl3d 3 c 9 pl5a 1 t pl4a 3 10 vccio1 1 vccio3 3 11 pl5b 1 c pl4c 3 t 12 gndio1 1 gndio3 3 13 pl5c 1 t pl4d 3 c 14 pl5d 1 gsrn c pl5b 3 gsrn 15 pl6a 1 t pl7b 3 16 pl6b 1 tsall c pl8c 3 tsall t 17 pl7a 1 t pl8d 3 c 18 pl7b 1 c pl9a 3 19 pl7c 1 t pl9c 3 20 pl7d 1 c pl10a 3 21 pl8a 1 t pl10c 3 22 pl8b 1 c pl11a 3 23 pl9a 1 t pl11c 3 24 vccio1 1 vccio3 3 25 gndio1 1 gndio3 3 26 tms 1 tms tms 2 tms 27 pl9b 1 c pb2c 2 28 tck 1 tck tck 2 tck 29 pb2a 1 t vccio2 2 30 pb2b 1 c gndio2 2 31 tdo 1 tdo tdo 2 tdo 32 pb2c 1 t pb4c 2 33 tdi 1 tdi tdi 2 tdi 34 pb2d 1 c pb4e 2 35 vcc - vcc - 36 pb3a 1 pclk1_1** t pb5b 2 pclk2_1** 37 pb3b 1 c pb5d 2 38 pb3c 1 pclk1_0** t pb6b 2 pclk2_0** 39 pb3d 1 c pb6c 2 40 gnd - gnd - 41 vccio1 1 vccio2 2
4-6 pinout information lattice semiconductor la-machxo automotive family data sheet 42 gndio1 1 gndio2 2 43 pb4a 1 t pb8b 2 44 pb4b 1 c pb8c 2 t 45 pb4c 1 t pb8d 2 c 46 pb4d 1 c pb9a 2 47 pb5a 1 pb9c 2 t 48* sleepn - sleepn sleepn - sleepn 49 pb5c 1 t pb9d 2 c 50 pb5d 1 c pb9f 2 51 pr9b 0 c pr11d 1 c 52 pr9a 0 t pr11b 1 c 53 pr8b 0 c pr11c 1 t 54 pr8a 0 t pr11a 1 t 55 pr7d 0 c pr10d 1 c 56 pr7c 0 t pr10c 1 t 57 pr7b 0 c pr10b 1 c 58 pr7a 0 t pr10a 1 t 59 pr6b 0 c pr9d 1 60 vccio0 0 vccio1 1 61 pr6a 0 t pr9b 1 62 gndio0 0 gndio1 1 63 pr5d 0 c pr7b 1 64 pr5c 0 t pr6c 1 65 pr5b 0 c pr6b 1 66 pr5a 0 t pr5d 1 67 pr4b 0 c pr5b 1 68 pr4a 0 t pr4d 1 69 pr3d 0 c pr4b 1 70 pr3c 0 t pr3d 1 71 pr3b 0 c pr3b 1 72 pr3a 0 t pr2d 1 73 pr2b 0 c pr2b 1 74 vccio0 0 vccio1 1 75 gndio0 0 gndio1 1 76 pr2a 0 t pt9f 0 c 77 pt5c 0 pt9e 0 t 78 pt5b 0 c pt9c 0 79 pt5a 0 t pt9a 0 80 pt4f 0 c vccio0 0 81 pt4e 0 t gndio0 0 82 pt4d 0 c pt7e 0 la-machxo256 and la-machxo640 logic signal connections: 100 tqfp (cont.) pin number lamxo256 lamxo640 ball function bank dual function differential ball function bank dual function differential
4-7 pinout information lattice semiconductor la-machxo automotive family data sheet 83 pt4c 0 t pt7a 0 84 gnd - gnd - 85 pt4b 0 pclk0_1** c pt6b 0 pclk0_1** 86 pt4a 0 pclk0_0** t pt5b 0 pclk0_0** c 87 pt3d 0 c pt5a 0 t 88 vccaux - vccaux - 89 pt3c 0 t pt4f 0 90 vcc - vcc - 91 pt3b 0 c pt3f 0 92 vccio0 0 vccio0 0 93 gndio0 0 gndio0 0 94 pt3a 0 t pt3b 0 c 95 pt2f 0 c pt3a 0 t 96 pt2e 0 t pt2f 0 c 97 pt2d 0 c pt2e 0 t 98 pt2c 0 t pt2b 0 c 99 pt2b 0 c pt2c 0 100 pt2a 0 t pt2a 0 t * nc for ? devices. ** primary clock inputs are single-ended. la-machxo256 and la-machxo640 logic signal connections: 100 tqfp (cont.) pin number lamxo256 lamxo640 ball function bank dual function differential ball function bank dual function differential
4-8 pinout information lattice semiconductor la-machxo automotive family data sheet la-machxo1200 and la-machxo2280 logic signal connections: 100 tqfp pin number lamxo1200 lamxo2280 ball function bank dual function differential ball function bank dual function differential 1 pl2a 7 t pl2a 7 lum0_pllt_fb_a t 2 pl2b 7 c pl2b 7 lum0_pllc_fb_a c 3 pl3c 7 t pl3c 7 lum0_pllt_in_a t 4 pl3d 7 c pl3d 7 lum0_pllc_in_a c 5 pl4b 7 pl4b 7 6 vccio7 7 vccio7 7 7 pl6a 7 t* pl7a 7 t* 8 pl6b 7 gsrn c* pl7b 7 gsrn c* 9 gnd - gnd - 10 pl7c 7 t pl9c 7 t 11 pl7d 7 c pl9d 7 c 12 pl8c 7 t pl10c 7 t 13 pl8d 7 c pl10d 7 c 14 pl9c 6 pl11c 6 15 pl10a 6 t* pl13a 6 t* 16 pl10b 6 c* pl13b 6 c* 17 vcc - vcc - 18 pl11b 6 pl14d 6 c 19 pl11c 6 tsall pl14c 6 tsall t 20 vccio6 6 vccio6 6 21 pl13c 6 pl16c 6 22 pl14a 6 llm0_pllt_fb_a t* pl17a 6 llm0_pllt_fb_a t* 23 pl14b 6 llm0_pllc_fb_a c* pl17b 6 llm0_pllc_fb_a c* 24 pl15a 6 llm0_pllt_in_a t* pl18a 6 llm0_pllt_in_a t* 25 pl15b 6 llm0_pllc_in_a c* pl18b 6 llm0_pllc_in_a c* 26** gndio6 gndio5 - gndio6 gndio5 - 27 vccio5 5 vccio5 5 28 tms 5 tms tms 5 tms 29 tck 5 tck tck 5 tck 30 pb3b 5 pb3b 5 31 pb4a 5 t pb4a 5 t 32 pb4b 5 c pb4b 5 c 33 tdo 5 tdo tdo 5 tdo 34 tdi 5 tdi tdi 5 tdi 35 vcc - vcc - 36 vccaux - vccaux - 37 pb6e 5 t pb8e 5 t 38 pb6f 5 c pb8f 5 c 39 pb7b 4 pclk4_1*** pb10f 4 pclk4_1*** 40 pb7f 4 pclk4_0*** pb10b 4 pclk4_0***
4-9 pinout information lattice semiconductor la-machxo automotive family data sheet 41 gnd - gnd - 42 pb9a 4 t pb12a 4 t 43 pb9b 4 c pb12b 4 c 44 vccio4 4 vccio4 4 45 pb10a 4 t pb13a 4 t 46 pb10b 4 c pb13b 4 c 47 nc - nc nc - nc 48 pb11a 4 t pb16a 4 t 49 pb11b 4 c pb16b 4 c 50** gndio3 gndio4 - gndio3 gndio4 - 51 pr16b 3 pr19b 3 52 pr15b 3 c* pr18b 3 c* 53 pr15a 3 t* pr18a 3 t* 54 pr14b 3 c* pr17b 3 c* 55 pr14a 3 t* pr17a 3 t* 56 vccio3 3 vccio3 3 57 pr12b 3 c* pr15b 3 c* 58 pr12a 3 t* pr15a 3 t* 59 gnd - gnd - 60 pr10b 3 c* pr13b 3 c* 61 pr10a 3 t* pr13a 3 t* 62 pr9b 3 c* pr11b 3 c* 63 pr9a 3 t* pr11a 3 t* 64 pr8b 2 c* pr10b 2 c* 65 pr8a 2 t* pr10a 2 t* 66 vcc - vcc - 67 pr6c 2 pr8c 2 68 pr6b 2 c* pr8b 2 c* 69 pr6a 2 t* pr8a 2 t* 70 vccio2 2 vccio2 2 71 pr4d 2 pr5d 2 72 pr4b 2 c* pr5b 2 c* 73 pr4a 2 t* pr5a 2 t* 74 pr2b 2 c pr3b 2 c* 75 pr2a 2 t pr3a 2 t* 76** gndio1 gndio2 - gndio1 gndio2 - 77 pt11c 1 pt15c 1 78 pt11b 1 c pt14b 1 c 79 pt11a 1 t pt14a 1 t la-machxo1200 and la-machxo2280 logic signal connections: 100 tqfp (cont.) pin number lamxo1200 lamxo2280 ball function bank dual function differential ball function bank dual function differential
4-10 pinout information lattice semiconductor la-machxo automotive family data sheet 80 vccio1 1 vccio1 1 81 pt9e 1 pt12d 1 c 82 pt9a 1 pt12c 1 t 83 gnd - gnd - 84 pt8b 1 c pt11b 1 c 85 pt8a 1 t pt11a 1 t 86 pt7d 1 pclk1_1*** pt10b 1 pclk1_1*** 87 pt6f 0 pclk1_0*** pt9b 1 pclk1_0*** 88 pt6d 0 c pt8f 0 c 89 pt6c 0 t pt8e 0 t 90 vccaux - vccaux - 91 vcc - vcc - 92 pt5b 0 pt6d 0 93 pt4b 0 pt6f 0 94 vccio0 0 vccio0 0 95 pt3d 0 c pt4b 0 c 96 pt3c 0 t pt4a 0 t 97 pt3b 0 pt3b 0 98 pt2b 0 c pt2b 0 c 99 pt2a 0 t pt2a 0 t 100** gndio0 gndio7 - gndio0 gndio7 - *supports true lvds outputs. **double bonded to the pin. *** primary clock inputs are single-ended. la-machxo1200 and la-machxo2280 logic signal connections: 100 tqfp (cont.) pin number lamxo1200 lamxo2280 ball function bank dual function differential ball function bank dual function differential
4-11 pinout information lattice semiconductor la-machxo automotive family data sheet la-machxo640, la-machxo1200 and la-machxo2280 logic signal connections: 144 tqfp pin number lamxo640 lamxo1200 lamxo2280 ball function bank dual function differential ball function bank dual function differential ball function bank dual function differential 1 pl2a 3 t pl2a 7 t pl2a 7 lum0_pllt_fb_a t 2 pl2c 3 t pl2b 7 c pl2b 7 lum0_pllc_fb_a c 3 pl2b 3 c pl3a 7 t* pl3a 7 t* 4 pl3a 3 t pl3b 7 c* pl3b 7 c* 5 pl2d 3 c pl3c 7 t pl3c 7 lum0_pllt_in_a t 6 pl3b 3 c pl3d 7 c pl3d 7 lum0_pllc_in_a c 7 pl3c 3 t pl4a 7 t* pl4a 7 t* 8 pl3d 3 c pl4b 7 c* pl4b 7 c* 9 pl4a 3 pl4c 7 pl4c 7 10 vccio3 3 vccio7 7 vccio7 7 11 gndio3 3 gndio7 7 gndio7 7 12 pl4d 3 pl5c 7 pl6c 7 13 pl5a 3 t pl6a 7 t* pl7a 7 t* 14 pl5b 3 gsrn c pl6b 7 gsrn c* pl7b 7 gsrn c* 15 pl5d 3 pl6d 7 pl7d 7 16 gnd - gnd - gnd - 17 pl6c 3 t pl7c 7 t pl9c 7 t 18 pl6d 3 c pl7d 7 c pl9d 7 c 19 pl7a 3 t pl10a 6 t* pl13a 6 t* 20 pl7b 3 c pl10b 6 c* pl13b 6 c* 21 vcc - vcc - vcc - 22 pl8a 3 t pl11a 6 t* pl13d 6 23 pl8b 3 c pl11b 6 c* pl14d 6 c 24 pl8c 3 tsall pl11c 6 tsall pl14c 6 tsall t 25 pl9c 3 t pl12b 6 pl15b 6 26 vccio3 3 vccio6 6 vccio6 6 27 gndio3 3 gndio6 6 gndio6 6 28 pl9d 3 c pl13d 6 pl16d 6 29 pl10a 3 t pl14a 6 llm0_pllt_fb_a t* pl17a 6 llm0_pllt_fb_a t* 30 pl10b 3 c pl14b 6 llm0_pllc_fb_a c* pl17b 6 llm0_pllc_fb_a c* 31 pl10c 3 t pl14c 6 t pl17c 6 t 32 pl11a 3 t pl14d 6 c pl17d 6 c 33 pl10d 3 c pl15a 6 llm0_pllt_in_a t* pl18a 6 llm0_pllt_in_a t* 34 pl11c 3 t pl15b 6 llm0_pllc_in_a c* pl18b 6 llm0_pllc_in_a c* 35 pl11b 3 c pl16a 6 t pl19a 6 t 36 pl11d 3 c pl16b 6 c pl19b 6 c 37 gndio2 2 gndio5 5 gndio5 5 38 vccio2 2 vccio5 5 vccio5 5 39 tms 2 tms tms 5 tms tms 5 tms 40 pb2c 2 pb2c 5 t pb2a 5 t 41 pb3a 2 t pb2d 5 c pb2b 5 c 42 tck 2 tck tck 5 tck tck 5 tck 43 pb3b 2 c pb3a 5 t pb3a 5 t 44 pb3c 2 t pb3b 5 c pb3b 5 c 45 pb3d 2 c pb4a 5 t pb4a 5 t 46 pb4a 2 t pb4b 5 c pb4b 5 c 47 tdo 2 tdo tdo 5 tdo tdo 5 tdo 48 pb4b 2 c pb4d 5 pb4d 5 49 pb4c 2 t pb5a 5 t pb5a 5 t 50 pb4d 2 c pb5b 5 c pb5b 5 c
4-12 pinout information lattice semiconductor la-machxo automotive family data sheet 51 tdi 2 tdi tdi 5 tdi tdi 5 tdi 52 vcc - vcc - vcc - 53 vccaux - vccaux - vccaux - 54 pb5a 2 t pb6f 5 pb8f 5 55 pb5b 2 pclkt2_1*** c pb7b 4 pclk4_1*** pb10f 4 pclk4_1*** 56 pb5d 2 pb7c 4 t pb10c 4 t 57 pb6a 2 t pb7d 4 c pb10d 4 c 58 pb6b 2 pclkt2_0*** c pb7f 4 pclk4_0*** pb10b 4 pclk4_0*** 59 gnd - gnd - gnd - 60 pb7c 2 pb9a 4 t pb12a 4 t 61 pb7e 2 pb9b 4 c pb12b 4 c 62 pb8a 2 pb9e 4 pb12e 4 63 vccio2 2 vccio4 4 vccio4 4 64 gndio2 2 gndio4 4 gndio4 4 65 pb8c 2 t pb10a 4 t pb13a 4 t 66 pb8d 2 c pb10b 4 c pb13b 4 c 67 pb9a 2 t pb10c 4 t pb13c 4 t 68 pb9c 2 t pb10d 4 c pb13d 4 c 69 pb9b 2 c pb10f 4 pb14d 4 70** sleepn - sleepn nc - nc - 71 pb9d 2 c pb11c 4 t pb16c 4 t 72 pb9f 2 pb11d 4 c pb16d 4 c 73 pr11d 1 c pr16b 3 c pr20b 3 c 74 pr11b 1 c pr16a 3 t pr20a 3 t 75 pr11c 1 t pr15b 3 c* pr19b 3 c 76 pr10d 1 c pr15a 3 t* pr19a 3 t 77 pr11a 1 t pr14d 3 c pr17d 3 c 78 pr10b 1 c pr14c 3 t pr17c 3 t 79 pr10c 1 t pr14b 3 c* pr17b 3 c* 80 pr10a 1 t pr14a 3 t* pr17a 3 t* 81 pr9d 1 pr13d 3 pr16d 3 82 vccio1 1 vccio3 3 vccio3 3 83 gndio1 1 gndio3 3 gndio3 3 84 pr9a 1 pr12b 3 c* pr15b 3 c* 85 pr8c 1 pr12a 3 t* pr15a 3 t* 86 pr8a 1 pr11b 3 c* pr14b 3 c* 87 pr7d 1 pr11a 3 t* pr14a 3 t* 88 gnd - gnd - gnd - 89 pr7b 1 c pr10b 3 c* pr13b 3 c* 90 pr7a 1 t pr10a 3 t* pr13a 3 t* 91 pr6d 1 c pr8b 2 c* pr10b 2 c* 92 pr6c 1 t pr8a 2 t* pr10a 2 t* 93 vcc - vcc - vcc - 94 pr5d 1 pr6b 2 c* pr8b 2 c* 95 pr5b 1 pr6a 2 t* pr8a 2 t* 96 pr4d 1 pr5b 2 c* pr7b 2 c* 97 pr4b 1 c pr5a 2 t* pr7a 2 t* 98 vccio1 1 vccio2 2 vccio2 2 99 gndio1 1 gndio2 2 gndio2 2 100 pr4a 1 t pr4c 2 pr5c 2 la-machxo640, la-machxo1200 and la-machxo2280 logic signal connections: 144 tqfp (cont.) pin number lamxo640 lamxo1200 lamxo2280 ball function bank dual function differential ball function bank dual function differential ball function bank dual function differential
4-13 pinout information lattice semiconductor la-machxo automotive family data sheet 101 pr3d 1 c pr4b 2 c* pr5b 2 c* 102 pr3c 1 t pr4a 2 t* pr5a 2 t* 103 pr3b 1 c pr3d 2 c pr4d 2 c 104 pr2d 1 c pr3c 2 t pr4c 2 t 105 pr3a 1 t pr3b 2 c* pr4b 2 c* 106 pr2b 1 c pr3a 2 t* pr4a 2 t* 107 pr2c 1 t pr2b 2 c pr3b 2 c* 108 pr2a 1 t pr2a 2 t pr3a 2 t* 109 pt9f 0 c pt11d 1 c pt16d 1 c 110 pt9d 0 c pt11c 1 t pt16c 1 t 111 pt9e 0 t pt11b 1 c pt16b 1 c 112 pt9b 0 c pt11a 1 t pt16a 1 t 113 pt9c 0 t pt10f 1 c pt15d 1 c 114 pt9a 0 t pt10e 1 t pt15c 1 t 115 pt8c 0 pt10d 1 c pt14b 1 c 116 pt8b 0 c pt10c 1 t pt14a 1 t 117 vccio0 0 vccio1 1 vccio1 1 118 gndio0 0 gndio1 1 gndio1 1 119 pt8a 0 t pt9f 1 c pt12f 1 c 120 pt7e 0 pt9e 1 t pt12e 1 t 121 pt7c 0 pt9b 1 c pt12d 1 c 122 pt7a 0 pt9a 1 t pt12c 1 t 123 gnd - gnd - gnd - 124 pt6b 0 pclk0_1*** c pt7d 1 pclk1_1*** pt10b 1 pclk1_1*** 125 pt6a 0 t pt7b 1 c pt9d 1 c 126 pt5c 0 pt7a 1 t pt9c 1 t 127 pt5b 0 pclk0_0*** pt6f 0 pclk1_0*** pt9b 1 pclk1_0*** 128 vccaux - vccaux - vccaux - 129 vcc - vcc - vcc - 130 pt4d 0 pt5d 0 c pt7b 0 c 131 pt4b 0 c pt5c 0 t pt7a 0 t 132 pt4a 0 t pt5b 0 c pt6d 0 133 pt3f 0 pt5a 0 t pt6e 0 t 134 pt3d 0 pt4b 0 pt6f 0 c 135 vccio0 0 vccio0 0 vccio0 0 136 gndio0 0 gndio0 0 gndio0 0 137 pt3b 0 c pt3d 0 c pt4b 0 t 138 pt2f 0 c pt3c 0 t pt4a 0 c 139 pt3a 0 t pt3b 0 c pt3b 0 c 140 pt2d 0 c pt3a 0 t pt3a 0 t 141 pt2e 0 t pt2d 0 c pt2d 0 c 142 pt2b 0 c pt2c 0 t pt2c 0 t 143 pt2c 0 t pt2b 0 c pt2b 0 c 144 pt2a 0 t pt2a 0 t pt2a 0 t *supports true lvds outputs. **nc for ? devices. ***primary clock inputs arer single-ended. la-machxo640, la-machxo1200 and la-machxo2280 logic signal connections: 144 tqfp (cont.) pin number lamxo640 lamxo1200 lamxo2280 ball function bank dual function differential ball function bank dual function differential ball function bank dual function differential
4-14 pinout information lattice semiconductor la-machxo automotive family data sheet la-machxo640, la-machxo1200 and la-machxo2280 logic signal connections: 256 ftbga lamxo640 lamxo1200 lamxo2280 ball number ball function bank dual function differential ball number ball function bank dual function differential ball number ball function bank dual function differential gnd gndio3 3 gnd gndio7 7 gnd gndio7 7 vccio3 vccio3 3 vccio7 vccio7 7 vccio7 vccio7 7 e4 nc e4 pl2a 7 t e4 pl2a 7 lum0_pllt_fb_a t e5 nc e5 pl2b 7 c e5 pl2b 7 lum0_pllc_fb_a c f5 nc f5 pl3a 7 t** f5 pl3a 7 t** f6 nc f6 pl3b 7 c** f6 pl3b 7 c** f3 pl3a 3 t f3 pl3c 7 t f3 pl3c 7 lum0_pllt_in_a t f4 pl3b 3 c f4 pl3d 7 c f4 pl3d 7 lum0_pllc_in_a c e3 pl2c 3 t e3 pl4a 7 t** e3 pl4a 7 t** e2 pl2d 3 c e2 pl4b 7 c** e2 pl4b 7 c** c3 nc c3 pl4c 7 t c3 pl4c 7 t c2 nc c2 pl4d 7 c c2 pl4d 7 c b1 pl2a 3 t b1 pl5a 7 t** b1 pl5a 7 t** c1 pl2b 3 c c1 pl5b 7 c** c1 pl5b 7 c** vccio3 vccio3 3 vccio7 vccio7 7 vccio7 vccio7 7 gnd gndio3 3 gnd gndio7 7 gnd gndio7 7 d2 pl3c 3 t d2 pl5c 7 t d2 pl6c 7 t d1 pl3d 3 c d1 pl5d 7 c d1 pl6d 7 c f2 pl5a 3 t f2 pl6a 7 t** f2 pl7a 7 t** g2 pl5b 3 gsrn c g2 pl6b 7 gsrn c** g2 pl7b 7 gsrn c** e1 pl4a 3 t e1 pl6c 7 t e1 pl7c 7 t f1 pl4b 3 c f1 pl6d 7 c f1 pl7d 7 c g4 nc g4 pl7a 7 t** g4 pl8a 7 t** g5 nc g5 pl7b 7 c** g5 pl8b 7 c** gnd gnd - gnd gnd - gnd gnd - g3 pl4c 3 t g3 pl7c 7 t g3 pl8c 7 t h3 pl4d 3 c h3 pl7d 7 c h3 pl8d 7 c h4 nc h4 pl8a 7 t** h4 pl9a 7 t** h5 nc h5 pl8b 7 c** h5 pl9b 7 c** - - vccio7 vccio7 7 vccio7 vccio7 7 - - gnd gndio7 7 gnd gndio7 7 g1 pl5c 3 t g1 pl8c 7 t g1 pl10c 7 t h1 pl5d 3 c h1 pl8d 7 c h1 pl10d 7 c h2 pl6a 3 t h2 pl9a 6 t** h2 pl11a 6 t** j2 pl6b 3 c j2 pl9b 6 c** j2 pl11b 6 c** j3 pl7c 3 t j3 pl9c 6 t j3 pl11c 6 t k3 pl7d 3 c k3 pl9d 6 c k3 pl11d 6 c j1 pl6c 3 t j1 pl10a 6 t** j1 pl12a 6 t** - - vccio6 vccio6 6 vccio6 vccio6 6 - - gnd gndio6 6 gnd gndio6 6 k1 pl6d 3 c k1 pl10b 6 c** k1 pl12b 6 c** k2 pl9a 3 t k2 pl10c 6 t k2 pl12c 6 t l2 pl9b 3 c l2 pl10d 6 c l2 pl12d 6 c l1 pl7a 3 t l1 pl11a 6 t** l1 pl13a 6 t** m1 pl7b 3 c m1 pl11b 6 c** m1 pl13b 6 c** p1 pl8d 3 c p1 pl11d 6 c p1 pl14d 6 c n1 pl8c 3 tsall t n1 pl11c 6 tsall t n1 pl14c 6 tsall t l3 pl10a 3 t l3 pl12a 6 t** l3 pl15a 6 t** m3 pl10b 3 c m3 pl12b 6 c** m3 pl15b 6 c** m2 pl9c 3 t m2 pl12c 6 t m2 pl15c 6 t n2 pl9d 3 c n2 pl12d 6 c n2 pl15d 6 c vccio3 vccio3 3 vccio6 vccio6 6 vccio6 vccio6 6 gnd gndio3 3 gnd gndio6 6 gnd gndio6 6
4-15 pinout information lattice semiconductor la-machxo automotive family data sheet j4 pl8a 3 t j4 pl13a 6 t** j4 pl16a 6 t** j5 pl8b 3 c j5 pl13b 6 c** j5 pl16b 6 c** r1 pl11a 3 t r1 pl13c 6 t r1 pl16c 6 t r2 pl11b 3 c r2 pl13d 6 c r2 pl16d 6 c - - - - - - gnd gnd - k5 nc k5 pl14a 6 llm0_pllt_fb_a t** k5 pl17a 6 llm0_pllt_fb_a t** k4 nc k4 pl14b 6 llm0_pllc_fb_a c** k4 pl17b 6 llm0_pllc_fb_a c** l5 pl10c 3 t l5 pl14c 6 t l5 pl17c 6 t l4 pl10d 3 c l4 pl14d 6 c l4 pl17d 6 c m5 nc m5 pl15a 6 llm0_pllt_in_a t** m5 pl18a 6 llm0_pllt_in_a t** m4 nc m4 pl15b 6 llm0_pllc_in_a c** m4 pl18b 6 llm0_pllc_in_a c** n4 pl11c 3 t n4 pl16a 6 t n4 pl19a 6 t n3 pl11d 3 c n3 pl16b 6 c n3 pl19b 6 c vccio3 vccio3 3 vccio6 vccio6 6 vccio6 vccio6 6 gnd gndio3 3 gnd gndio6 6 gnd gndio6 6 gnd gndio2 2 gnd gndio5 5 gnd gndio5 5 vccio2 vccio2 2 vccio5 vccio5 5 vccio5 vccio5 5 p4 tms 2 tms p4 tms 5 tms p4 tms 5 tms p2 nc p2 pb2a 5 t p2 pb2a 5 t p3 nc p3 pb2b 5 c p3 pb2b 5 c n5 nc n5 pb2c 5 t n5 pb2c 5 t r3 tck 2 tck r3 tck 5 tck r3 tck 5 tck n6 nc n6 pb2d 5 c n6 pb2d 5 c t2 pb2a 2 t t2 pb3a 5 t t2 pb3a 5 t t3 pb2b 2 c t3 pb3b 5 c t3 pb3b 5 c r4 pb2c 2 t r4 pb3c 5 t r4 pb3c 5 t r5 pb2d 2 c r5 pb3d 5 c r5 pb3d 5 c p5 pb3a 2 t p5 pb4a 5 t p5 pb4a 5 t p6 pb3b 2 c p6 pb4b 5 c p6 pb4b 5 c t5 pb3c 2 t t5 pb4c 5 t t5 pb4c 5 t m6 tdo 2 tdo m6 tdo 5 tdo m6 tdo 5 tdo t4 pb3d 2 c t4 pb4d 5 c t4 pb4d 5 c r6 pb4a 2 t r6 pb5a 5 t r6 pb5a 5 t gnd gndio2 2 gnd gndio5 5 gnd gndio5 5 vccio2 vccio2 2 vccio5 vccio5 5 vccio5 vccio5 5 t6 pb4b 2 c t6 pb5b 5 c t6 pb5b 5 c n7 tdi 2 tdi n7 tdi 5 tdi n7 tdi 5 tdi t8 pb4c 2 t t8 pb5c 5 t t8 pb6a 5 t t7 pb4d 2 c t7 pb5d 5 c t7 pb6b 5 c m7 nc m7 pb6a 5 t m7 pb7c 5 t m8 nc m8 pb6b 5 c m8 pb7d 5 c t9 vccaux - t9 vccaux - t9 vccaux - r7 pb4e 2 t r7 pb6c 5 t r7 pb8c 5 t r8 pb4f 2 c r8 pb6d 5 c r8 pb8d 5 c - - vccio5 vccio5 5 vccio5 vccio5 5 - - gnd gndio5 5 gnd gndio5 5 p7 pb5c 2 t p7 pb6e 5 t p7 pb9a 4 t p8 pb5d 2 c p8 pb6f 5 c p8 pb9b 4 c n8 pb5a 2 t n8 pb7a 4 t n8 pb10e 4 t n9 pb5b 2 pclk2_1**** c n9 pb7b 4 pclk4_1**** c n9 pb10f 4 pclk4_1**** c p10 pb7b 2 c p10 pb7d 4 c p10 pb10d 4 c p9 pb7a 2 t p9 pb7c 4 t p9 pb10c 4 t m9 pb6b 2 pclk2_0**** c m9 pb7f 4 pclk4_0**** c m9 pb10b 4 pclk4_0**** c la-machxo640, la-machxo1200 and la-machxo2280 logic signal connections: 256 ftbga (cont.) lamxo640 lamxo1200 lamxo2280 ball number ball function bank dual function differential ball number ball function bank dual function differential ball number ball function bank dual function differential
4-16 pinout information lattice semiconductor la-machxo automotive family data sheet - - vccio4 vccio4 4 vccio4 vccio4 4 - - gnd gndio4 4 gnd gndio4 4 m10 pb6a 2 t m10 pb7e 4 t m10 pb10a 4 t r9 pb6c 2 t r9 pb8a 4 t r9 pb11c 4 t r10 pb6d 2 c r10 pb8b 4 c r10 pb11d 4 c t10 pb7c 2 t t10 pb8c 4 t t10 pb12a 4 t t11 pb7d 2 c t11 pb8d 4 c t11 pb12b 4 c n10 nc n10 pb8e 4 t n10 pb12c 4 t n11 nc n11 pb8f 4 c n11 pb12d 4 c vccio2 vccio2 2 vccio4 vccio4 4 vccio4 vccio4 4 gnd gndio2 2 gnd gndio4 4 gnd gndio4 4 r11 pb7e 2 t r11 pb9a 4 t r11 pb13a 4 t r12 pb7f 2 c r12 pb9b 4 c r12 pb13b 4 c p11 pb8a 2 t p11 pb9c 4 t p11 pb13c 4 t p12 pb8b 2 c p12 pb9d 4 c p12 pb13d 4 c t13 pb8c 2 t t13 pb9e 4 t t13 pb14a 4 t t12 pb8d 2 c t12 pb9f 4 c t12 pb14b 4 c r13 pb9a 2 t r13 pb10a 4 t r13 pb14c 4 t r14 pb9b 2 c r14 pb10b 4 c r14 pb14d 4 c gnd gnd - gnd gnd - gnd gnd - t14 pb9c 2 t t14 pb10c 4 t t14 pb15a 4 t t15 pb9d 2 c t15 pb10d 4 c t15 pb15b 4 c p13*** sleepn - sleepn p13 nc - p13 nc - p14 pb9f 2 p14 pb10f 4 p14 pb15d 4 r15 nc r15 pb11a 4 t r15 pb16a 4 t r16 nc r16 pb11b 4 c r16 pb16b 4 c p15 nc p15 pb11c 4 t p15 pb16c 4 t p16 nc p16 pb11d 4 c p16 pb16d 4 c vccio2 vccio2 2 vccio4 vccio4 4 vccio4 vccio4 4 gnd gndio2 2 gnd gndio4 4 gnd gndio4 4 gnd gndio1 1 gnd gndio3 3 gnd gndio3 3 vccio1 vccio1 1 vccio3 vccio3 3 vccio3 vccio3 3 m11 nc m11 pr16b 3 c m11 pr20b 3 c l11 nc l11 pr16a 3 t l11 pr20a 3 t n12 nc n12 pr15b 3 c** n12 pr18b 3 c** n13 nc n13 pr15a 3 t** n13 pr18a 3 t** m13 nc m13 pr14d 3 c m13 pr17d 3 c m12 nc m12 pr14c 3 t m12 pr17c 3 t n14 pr11d 1 c n14 pr14b 3 c** n14 pr17b 3 c** n15 pr11c 1 t n15 pr14a 3 t** n15 pr17a 3 t** l13 pr11b 1 c l13 pr13d 3 c l13 pr16d 3 c l12 pr11a 1 t l12 pr13c 3 t l12 pr16c 3 t m14 pr10b 1 c m14 pr13b 3 c** m14 pr16b 3 c** vccio1 vccio1 1 vccio3 vccio3 3 vccio3 vccio3 3 gnd gndio1 1 gnd gndio3 3 gnd gndio3 3 l14 pr10a 1 t l14 pr13a 3 t** l14 pr16a 3 t** n16 pr10d 1 c n16 pr12d 3 c n16 pr15d 3 c m16 pr10c 1 t m16 pr12c 3 t m16 pr15c 3 t m15 pr9d 1 c m15 pr12b 3 c** m15 pr15b 3 c** l15 pr9c 1 t l15 pr12a 3 t** l15 pr15a 3 t** l16 pr9b 1 c l16 pr11d 3 c l16 pr14d 3 c k16 pr9a 1 t k16 pr11c 3 t k16 pr14c 3 t k13 pr8d 1 c k13 pr11b 3 c** k13 pr14b 3 c** la-machxo640, la-machxo1200 and la-machxo2280 logic signal connections: 256 ftbga (cont.) lamxo640 lamxo1200 lamxo2280 ball number ball function bank dual function differential ball number ball function bank dual function differential ball number ball function bank dual function differential
4-17 pinout information lattice semiconductor la-machxo automotive family data sheet j13 pr8c 1 t j13 pr11a 3 t** j13 pr14a 3 t** gnd gnd - gnd gnd - gnd gnd - k14 pr8b 1 c k14 pr10d 3 c k14 pr13d 3 c j14 pr8a 1 t j14 pr10c 3 t j14 pr13c 3 t k15 pr7d 1 c k15 pr10b 3 c** k15 pr13b 3 c** j15 pr7c 1 t j15 pr10a 3 t** j15 pr13a 3 t** - - gnd gndio3 3 gnd gndio3 3 - - vccio3 vccio3 3 vccio3 vccio3 3 k12 nc k12 pr9d 3 c k12 pr11d 3 c j12 nc j12 pr9c 3 t j12 pr11c 3 t j16 pr7b 1 c j16 pr9b 3 c** j16 pr11b 3 c** h16 pr7a 1 t h16 pr9a 3 t** h16 pr11a 3 t** h15 pr6b 1 c h15 pr8d 2 c h15 pr10d 2 c g15 pr6a 1 t g15 pr8c 2 t g15 pr10c 2 t h14 pr5d 1 c h14 pr8b 2 c** h14 pr10b 2 c** g14 pr5c 1 t g14 pr8a 2 t** g14 pr10a 2 t** gnd gndio1 1 gnd gndio2 2 gnd gndio2 2 vccio1 vccio1 1 vccio2 vccio2 2 vccio2 vccio2 2 h13 pr6d 1 c h13 pr7d 2 c h13 pr9d 2 c h12 pr6c 1 t h12 pr7c 2 t h12 pr9c 2 t g13 pr4d 1 c g13 pr7b 2 c** g13 pr9b 2 c** g12 pr4c 1 t g12 pr7a 2 t** g12 pr9a 2 t** g16 pr5b 1 c g16 pr6d 2 c g16 pr7d 2 c f16 pr5a 1 t f16 pr6c 2 t f16 pr7c 2 t f15 pr4b 1 c f15 pr6b 2 c** f15 pr7b 2 c** e15 pr4a 1 t e15 pr6a 2 t** e15 pr7a 2 t** e16 pr3b 1 c e16 pr5d 2 c e16 pr6d 2 c d16 pr3a 1 t d16 pr5c 2 t d16 pr6c 2 t vccio1 vccio1 1 vccio2 vccio2 2 vccio2 vccio2 2 gnd gndio1 1 gnd gndio2 2 gnd gndio2 2 d15 pr2d 1 c d15 pr5b 2 c** d15 pr6b 2 c** c15 pr2c 1 t c15 pr5a 2 t** c15 pr6a 2 t** c16 pr2b 1 c c16 pr4d 2 c c16 pr5d 2 c b16 pr2a 1 t b16 pr4c 2 t b16 pr5c 2 t f14 pr3d 1 c f14 pr4b 2 c** f14 pr5b 2 c** e14 pr3c 1 t e14 pr4a 2 t** e14 pr5a 2 t** - - - - - - gnd gnd - f12 nc f12 pr3d 2 c f12 pr4d 2 c f13 nc f13 pr3c 2 t f13 pr4c 2 t e12 nc e12 pr3b 2 c** e12 pr4b 2 c** e13 nc e13 pr3a 2 t** e13 pr4a 2 t** d13 nc d13 pr2b 2 c d13 pr3b 2 c** d14 nc d14 pr2a 2 t d14 pr3a 2 t** vccio0 vccio0 0 vccio2 vccio2 2 vccio2 vccio2 2 gnd gndio0 0 gnd gndio2 2 gnd gndio2 2 gnd gndio0 0 gnd gndio1 1 gnd gndio1 1 vccio0 vccio0 0 vccio1 vccio1 1 vccio1 vccio1 1 b15 nc b15 pt11d 1 c b15 pt16d 1 c a15 nc a15 pt11c 1 t a15 pt16c 1 t c14 nc c14 pt11b 1 c c14 pt16b 1 c b14 nc b14 pt11a 1 t b14 pt16a 1 t c13 pt9f 0 c c13 pt10f 1 c c13 pt15d 1 c b13 pt9e 0 t b13 pt10e 1 t b13 pt15c 1 t la-machxo640, la-machxo1200 and la-machxo2280 logic signal connections: 256 ftbga (cont.) lamxo640 lamxo1200 lamxo2280 ball number ball function bank dual function differential ball number ball function bank dual function differential ball number ball function bank dual function differential
4-18 pinout information lattice semiconductor la-machxo automotive family data sheet e11 nc e11 pt10d 1 c e11 pt15b 1 c e10 nc e10 pt10c 1 t e10 pt15a 1 t d12 pt9d 0 c d12 pt10b 1 c d12 pt14d 1 c d11 pt9c 0 t d11 pt10a 1 t d11 pt14c 1 t a14 pt7f 0 c a14 pt9f 1 c a14 pt14b 1 c a13 pt7e 0 t a13 pt9e 1 t a13 pt14a 1 t c12 pt8b 0 c c12 pt9d 1 c c12 pt13d 1 c c11 pt8a 0 t c11 pt9c 1 t c11 pt13c 1 t - - vccio1 vccio1 1 vccio1 vccio1 1 - - gnd gndio1 1 gnd gndio1 1 b12 pt7b 0 c b12 pt9b 1 c b12 pt12d 1 c b11 pt7a 0 t b11 pt9a 1 t b11 pt12c 1 t a12 pt7d 0 c a12 pt8f 1 c a12 pt12b 1 c a11 pt7c 0 t a11 pt8e 1 t a11 pt12a 1 t gnd gnd - gnd gnd - gnd gnd - b10 pt5d 0 c b10 pt8d 1 c b10 pt11b 1 c b9 pt5c 0 t b9 pt8c 1 t b9 pt11a 1 t d10 pt8d 0 c d10 pt8b 1 c d10 pt10f 1 c d9 pt8c 0 t d9 pt8a 1 t d9 pt10e 1 t - - vccio1 vccio1 1 vccio1 vccio1 1 - - gnd gndio1 1 gnd gndio1 1 c10 pt6d 0 c c10 pt7f 1 c c10 pt10d 1 c c9 pt6c 0 t c9 pt7e 1 t c9 pt10c 1 t a9 pt6b 0 pclk0_1**** c a9 pt7d 1 pclk1_1**** c a9 pt10b 1 pclk1_1**** c a10 pt6a 0 t a10 pt7c 1 t a10 pt10a 1 t e9 pt9b 0 c e9 pt7b 1 c e9 pt9d 1 c e8 pt9a 0 t e8 pt7a 1 t e8 pt9c 1 t d7 pt5b 0 pclk0_0**** c d7 pt6f 0 pclk1_0**** c d7 pt9b 1 pclk1_0**** c d8 pt5a 0 t d8 pt6e 0 t d8 pt9a 1 t vccio0 vccio0 0 vccio0 vccio0 0 vccio0 vccio0 0 gnd gndio0 0 gnd gndio0 0 gnd gndio0 0 c8 pt4f 0 c c8 pt6d 0 c c8 pt8d 0 c b8 pt4e 0 t b8 pt6c 0 t b8 pt8c 0 t a8 vccaux - a8 vccaux - a8 vccaux - a7 pt4d 0 c a7 pt6b 0 c a7 pt7d 0 c a6 pt4c 0 t a6 pt6a 0 t a6 pt7c 0 t b7 pt4b 0 c b7 pt5f 0 c b7 pt7b 0 c b6 pt4a 0 t b6 pt5e 0 t b6 pt7a 0 t c6 pt3c 0 t c6 pt5c 0 t c6 pt6a 0 t c7 pt3d 0 c c7 pt5d 0 c c7 pt6b 0 c a5 pt3e 0 t a5 pt5a 0 t a5 pt6c 0 t a4 pt3f 0 c a4 pt5b 0 c a4 pt6d 0 c e7 nc e7 pt4c 0 t e7 pt6e 0 t e6 nc e6 pt4d 0 c e6 pt6f 0 c b5 pt3b 0 c b5 pt3f 0 c b5 pt5d 0 c b4 pt3a 0 t b4 pt3e 0 t b4 pt5c 0 t d5 pt2d 0 c d5 pt3d 0 c d5 pt5b 0 c d6 pt2c 0 t d6 pt3c 0 t d6 pt5a 0 t c4 pt2e 0 t c4 pt4a 0 t c4 pt4a 0 t c5 pt2f 0 c c5 pt4b 0 c c5 pt4b 0 c - - - - - - gnd gnd - d4 nc d4 pt2d 0 c d4 pt3d 0 c d3 nc d3 pt2c 0 t d3 pt3c 0 t la-machxo640, la-machxo1200 and la-machxo2280 logic signal connections: 256 ftbga (cont.) lamxo640 lamxo1200 lamxo2280 ball number ball function bank dual function differential ball number ball function bank dual function differential ball number ball function bank dual function differential
4-19 pinout information lattice semiconductor la-machxo automotive family data sheet a3 pt2b 0 c a3 pt3b 0 c a3 pt3b 0 c a2 pt2a 0 t a2 pt3a 0 t a2 pt3a 0 t b3 nc b3 pt2b 0 c b3 pt2d 0 c b2 nc b2 pt2a 0 t b2 pt2c 0 t vccio0 vccio0 0 vccio0 vccio0 0 vccio0 vccio0 0 gnd gndio0 0 gnd gndio0 0 gnd gndio0 0 a1 gnd - a1 gnd - a1 gnd - a16 gnd - a16 gnd - a16 gnd - f11 gnd - f11 gnd - f11 gnd - g8 gnd - g8 gnd - g8 gnd - g9 gnd - g9 gnd - g9 gnd - h7 gnd - h7 gnd - h7 gnd - h8 gnd - h8 gnd - h8 gnd - h9 gnd - h9 gnd - h9 gnd - h10 gnd - h10 gnd - h10 gnd - j7 gnd - j7 gnd - j7 gnd - j8 gnd - j8 gnd - j8 gnd - j9 gnd - j9 gnd - j9 gnd - j10 gnd - j10 gnd - j10 gnd - k8 gnd - k8 gnd - k8 gnd - k9 gnd - k9 gnd - k9 gnd - l6 gnd - l6 gnd - l6 gnd - t1 gnd - t1 gnd - t1 gnd - t16 gnd - t16 gnd - t16 gnd - g7 vcc - g7 vcc - g7 vcc - g10 vcc - g10 vcc - g10 vcc - k7 vcc - k7 vcc - k7 vcc - k10 vcc - k10 vcc - k10 vcc - h6 vccio3 3 h6 vccio7 7 h6 vccio7 7 g6 vccio3 3 g6 vccio7 7 g6 vccio7 7 k6 vccio3 3 k6 vccio6 6 k6 vccio6 6 j6 vccio3 3 j6 vccio6 6 j6 vccio6 6 l8 vccio2 2 l8 vccio5 5 l8 vccio5 5 l7 vccio2 2 l7 vccio5 5 l7 vccio5 5 l9 vccio2 2 l9 vccio4 4 l9 vccio4 4 l10 vccio2 2 l10 vccio4 4 l10 vccio4 4 k11 vccio1 1 k11 vccio3 3 k11 vccio3 3 j11 vccio1 1 j11 vccio3 3 j11 vccio3 3 h11 vccio1 1 h11 vccio2 2 h11 vccio2 2 g11 vccio1 1 g11 vccio2 2 g11 vccio2 2 f9 vccio0 0 f9 vccio1 1 f9 vccio1 1 f10 vccio0 0 f10 vccio1 1 f10 vccio1 1 f8 vccio0 0 f8 vccio0 0 f8 vccio0 0 f7 vccio0 0 f7 vccio0 0 f7 vccio0 0 * lcmxo640 only. ** supports true lvds outputs. *** nc for ? devices. **** primary clock inputs are single-ended. la-machxo640, la-machxo1200 and la-machxo2280 logic signal connections: 256 ftbga (cont.) lamxo640 lamxo1200 lamxo2280 ball number ball function bank dual function differential ball number ball function bank dual function differential ball number ball function bank dual function differential
4-20 pinout information lattice semiconductor la-machxo automotive family data sheet la-machxo2280 logic signal connections: 324 ftbga lamxo2280 ball number ball function bank dual function differential gnd gndio7 7 vccio7 vccio7 7 d4 pl2a 7 lum0_pllt_fb_a t f5 pl2b 7 lum0_pllc_fb_a c b3 pl3a 7 t* c3 pl3b 7 c* e4 pl3c 7 lum0_pllt_in_a t g6 pl3d 7 lum0_pllc_in_a c a1 pl4a 7 t* b1 pl4b 7 c* f4 pl4c 7 t vcc vcc - e3 pl4d 7 c d2 pl5a 7 t* d3 pl5b 7 c* g5 pl5c 7 t f3 pl5d 7 c c2 pl6a 7 t* vccio7 vccio7 7 gnd gndio7 7 c1 pl6b 7 c* h5 pl6c 7 t g4 pl6d 7 c e2 pl7a 7 t* d1 pl7b 7 gsrn c* j6 pl7c 7 t h4 pl7d 7 c f2 pl8a 7 t* e1 pl8b 7 c* gnd gnd - j3 pl8c 7 t j5 pl8d 7 c g3 pl9a 7 t* h3 pl9b 7 c* k3 pl9c 7 t k5 pl9d 7 c f1 pl10a 7 t* vccio7 vccio7 7 gnd gndio7 7 g1 pl10b 7 c* k4 pl10c 7 t k6 pl10d 7 c
4-21 pinout information lattice semiconductor la-machxo automotive family data sheet g2 pl11a 6 t* h2 pl11b 6 c* l3 pl11c 6 t l5 pl11d 6 c h1 pl12a 6 t* vccio6 vccio6 6 gnd gndio6 6 j2 pl12b 6 c* l4 pl12c 6 t l6 pl12d 6 c k2 pl13a 6 t* k1 pl13b 6 c* j1 pl13c 6 t vcc vcc - l2 pl13d 6 c m5 pl14d 6 c m3 pl14c 6 tsall t l1 pl14b 6 c* m2 pl14a 6 t* m1 pl15a 6 t* n1 pl15b 6 c* m6 pl15c 6 t m4 pl15d 6 c vccio6 vccio6 6 gnd gndio6 6 p1 pl16a 6 t* p2 pl16b 6 c* n3 pl16c 6 t n4 pl16d 6 c gnd gnd - t1 pl17a 6 llm0_pllt_fb_a t* r1 pl17b 6 llm0_pllc_fb_a c* p3 pl17c 6 t n5 pl17d 6 c r3 pl18a 6 llm0_pllt_in_a t* r2 pl18b 6 llm0_pllc_in_a c* p4 pl19a 6 t n6 pl19b 6 c u1 pl20a 6 t vccio6 vccio6 6 gnd gndio6 6 gnd gndio5 5 vccio5 vccio5 5 la-machxo2280 logic signal connections: 324 ftbga (cont.) lamxo2280 ball number ball function bank dual function differential
4-22 pinout information lattice semiconductor la-machxo automotive family data sheet t2 pl20b 6 c p6 tms 5 tms v1 pb2a 5 t u2 pb2b 5 c t3 pb2c 5 t n7 tck 5 tck r4 pb2d 5 c r5 pb3a 5 t t4 pb3b 5 c vcc vcc - r6 pb3c 5 t p7 pb3d 5 c u3 pb4a 5 t t5 pb4b 5 c v2 pb4c 5 t n8 tdo 5 tdo v3 pb4d 5 c t6 pb5a 5 t gnd gndio5 5 vccio5 vccio5 5 u4 pb5b 5 c p8 pb5c 5 t t7 pb5d 5 c v4 tdi 5 tdi r8 pb6a 5 t n9 pb6b 5 c u5 pb6c 5 t v5 pb6d 5 c u6 pb7a 5 t vcc vcc - v6 pb7b 5 c p9 pb7c 5 t t8 pb7d 5 c u7 pb8a 5 t v7 pb8b 5 c m10 vccaux - u8 pb8c 5 t v8 pb8d 5 c vccio5 vccio5 5 gnd gndio5 5 t9 pb8e 5 t u9 pb8f 5 c v9 pb9a 4 t la-machxo2280 logic signal connections: 324 ftbga (cont.) lamxo2280 ball number ball function bank dual function differential
4-23 pinout information lattice semiconductor la-machxo automotive family data sheet v10 pb9b 4 c n10 pb9c 4 t r10 pb9d 4 c p10 pb10f 4 pclk4_1** c t10 pb10e 4 t u10 pb10d 4 c v11 pb10c 4 t u11 pb10b 4 pclk4_0** c vccio4 vccio4 4 gnd gndio4 4 t11 pb10a 4 t u12 pb11a 4 t r11 pb11b 4 c gnd gnd - t12 pb11c 4 t p11 pb11d 4 c v12 pb12a 4 t v13 pb12b 4 c r12 pb12c 4 t n11 pb12d 4 c u13 pb12e 4 t vccio4 vccio4 4 gnd gndio4 4 v14 pb12f 4 c t13 pb13a 4 t p12 pb13b 4 c r13 pb13c 4 t n12 pb13d 4 c v15 pb14a 4 t u14 pb14b 4 c v16 pb14c 4 t gnd gnd - t14 pb14d 4 c u15 pb15a 4 t v17 pb15b 4 c p13 nc - t15 pb15d 4 u16 pb16a 4 t v18 pb16b 4 c n13 pb16c 4 t r14 pb16d 4 c vccio4 vccio4 4 gnd gndio4 4 la-machxo2280 logic signal connections: 324 ftbga (cont.) lamxo2280 ball number ball function bank dual function differential
4-24 pinout information lattice semiconductor la-machxo automotive family data sheet gnd gndio3 3 vccio3 vccio3 3 p15 pr20b 3 c n14 pr20a 3 t n15 pr19b 3 c m13 pr19a 3 t r15 pr18b 3 c* t16 pr18a 3 t* n16 pr17d 3 c m14 pr17c 3 t u17 pr17b 3 c* vcc vcc - u18 pr17a 3 t* r17 pr16d 3 c r16 pr16c 3 t p16 pr16b 3 c* vccio3 vccio3 3 gnd gndio3 3 p17 pr16a 3 t* l13 pr15d 3 c m15 pr15c 3 t t17 pr15b 3 c* t18 pr15a 3 t* l14 pr14d 3 c l15 pr14c 3 t r18 pr14b 3 c* p18 pr14a 3 t* gnd gnd - k15 pr13d 3 c k13 pr13c 3 t n17 pr13b 3 c* n18 pr13a 3 t* k16 pr12d 3 c k14 pr12c 3 t m16 pr12b 3 c* l16 pr12a 3 t* gnd gndio3 3 vccio3 vccio3 3 j16 pr11d 3 c j14 pr11c 3 t m17 pr11b 3 c* l17 pr11a 3 t* j15 pr10d 2 c la-machxo2280 logic signal connections: 324 ftbga (cont.) lamxo2280 ball number ball function bank dual function differential
4-25 pinout information lattice semiconductor la-machxo automotive family data sheet j13 pr10c 2 t m18 pr10b 2 c* l18 pr10a 2 t* gnd gndio2 2 vccio2 vccio2 2 h16 pr9d 2 c h14 pr9c 2 t k18 pr9b 2 c* j18 pr9a 2 t* j17 pr8d 2 c vcc vcc - h18 pr8c 2 t h17 pr8b 2 c* g17 pr8a 2 t* h13 pr7d 2 c h15 pr7c 2 t g18 pr7b 2 c* f18 pr7a 2 t* g14 pr6d 2 c g16 pr6c 2 t vccio2 vccio2 2 gnd gndio2 2 e18 pr6b 2 c* f17 pr6a 2 t* g13 pr5d 2 c g15 pr5c 2 t e17 pr5b 2 c* e16 pr5a 2 t* gnd gnd - f15 pr4d 2 c e15 pr4c 2 t d17 pr4b 2 c* d18 pr4a 2 t* b18 pr3d 2 c c18 pr3c 2 t c16 pr3b 2 c* d16 pr3a 2 t* c17 pr2b 2 c d15 pr2a 2 t vccio2 vccio2 2 gnd gndio2 2 gnd gndio1 1 vccio1 vccio1 1 la-machxo2280 logic signal connections: 324 ftbga (cont.) lamxo2280 ball number ball function bank dual function differential
4-26 pinout information lattice semiconductor la-machxo automotive family data sheet e13 pt16d 1 c c15 pt16c 1 t f13 pt16b 1 c d14 pt16a 1 t a18 pt15d 1 c b17 pt15c 1 t a16 pt15b 1 c a17 pt15a 1 t vcc vcc - d13 pt14d 1 c f12 pt14c 1 t c14 pt14b 1 c e12 pt14a 1 t c13 pt13d 1 c b16 pt13c 1 t b15 pt13b 1 c a15 pt13a 1 t vccio1 vccio1 1 gnd gndio1 1 b14 pt12f 1 c a14 pt12e 1 t d12 pt12d 1 c f11 pt12c 1 t b13 pt12b 1 c a13 pt12a 1 t c12 pt11d 1 c gnd gnd - b12 pt11c 1 t e11 pt11b 1 c d11 pt11a 1 t c11 pt10f 1 c a12 pt10e 1 t vccio1 vccio1 1 gnd gndio1 1 f10 pt10d 1 c d10 pt10c 1 t b11 pt10b 1 pclk1_1*** c a11 pt10a 1 t e10 pt9d 1 c c10 pt9c 1 t d9 pt9b 1 pclk1_0*** c e9 pt9a 1 t b10 pt8f 0 c la-machxo2280 logic signal connections: 324 ftbga (cont.) lamxo2280 ball number ball function bank dual function differential
4-27 pinout information lattice semiconductor la-machxo automotive family data sheet a10 pt8e 0 t vccio0 vccio0 0 gnd gndio0 0 a9 pt8d 0 c c9 pt8c 0 t b9 pt8b 0 c f9 vccaux - a8 pt8a 0 t b8 pt7d 0 c c8 pt7c 0 t vcc vcc - a7 pt7b 0 c b7 pt7a 0 t a6 pt6a 0 t b6 pt6b 0 c d8 pt6c 0 t f8 pt6d 0 c c7 pt6e 0 t e8 pt6f 0 c d7 pt5d 0 c vccio0 vccio0 0 gnd gndio0 0 e7 pt5c 0 t a5 pt5b 0 c c6 pt5a 0 t b5 pt4a 0 t a4 pt4b 0 c d6 pt4c 0 t f7 pt4d 0 c b4 pt4e 0 t gnd gnd - c5 pt4f 0 c f6 pt3d 0 c e5 pt3c 0 t e6 pt3b 0 c d5 pt3a 0 t a3 pt2d 0 c c4 pt2c 0 t a2 pt2b 0 c b2 pt2a 0 t vccio0 vccio0 0 gnd gndio0 0 e14 gnd - la-machxo2280 logic signal connections: 324 ftbga (cont.) lamxo2280 ball number ball function bank dual function differential
4-28 pinout information lattice semiconductor la-machxo automotive family data sheet f16 gnd - h10 gnd - h11 gnd - h8 gnd - h9 gnd - j10 gnd - j11 gnd - j4 gnd - j8 gnd - j9 gnd - k10 gnd - k11 gnd - k17 gnd - k8 gnd - k9 gnd - l10 gnd - l11 gnd - l8 gnd - l9 gnd - n2 gnd - p14 gnd - p5 gnd - r7 gnd - f14 vcc - g11 vcc - g9 vcc - h7 vcc - l7 vcc - m9 vcc - h6 vccio7 7 j7 vccio7 7 m7 vccio6 6 k7 vccio6 6 m8 vccio5 5 r9 vccio5 5 m12 vccio4 4 m11 vccio4 4 l12 vccio3 3 k12 vccio3 3 j12 vccio2 2 h12 vccio2 2 g12 vccio1 1 g10 vccio1 1 la-machxo2280 logic signal connections: 324 ftbga (cont.) lamxo2280 ball number ball function bank dual function differential
4-29 pinout information lattice semiconductor la-machxo automotive family data sheet g8 vccio0 0 g7 vccio0 0 * supports true lvds outputs. ** primary clock inputs are single-ended. la-machxo2280 logic signal connections: 324 ftbga (cont.) lamxo2280 ball number ball function bank dual function differential
4-30 pinout information lattice semiconductor la-machxo automotive family data sheet thermal management thermal management is recommended as part of any sound fpga design methodology. to assess the thermal characteristics of a system, lattice speci?s a maximum allowable junction temperature in all device data sheets. designers must complete a thermal analysis of their speci? design to ensure that the device and package do not exceed the junction temperature limits. refer to the thermal management document to ?d the device/package speci? thermal values. for further information for further information regarding thermal management, refer to the following located on the lattice website at www .latticesemi.com . thermal management document technical note tn1090 - power estimation and management for machxo devices power calculator tool included with lattices isplever design tool, or as a standalone download from www .latticesemi.com/softw are
april 2006 data sheet ds1003 ?2006 lattice semiconductor corp. all lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www .latticesemi.com/legal. all other brand or product names are trademarks or registered trademarks of their respective holders. the speci?ations and information herein are subject to change without notice. www.latticesemi.com 5-1 ds1003 ordering information_01.0 part number description ordering information part number luts supply voltage i/os grade package pins temp. lamxo256c-3tn100e 256 1.8v/2.5v/3.3v 78 -3 lead-free tqfp 100 auto LAMXO640C-3TN100E 640 1.8v/2.5v/3.3v 74 -3 lead-free tqfp 100 auto lamxo640c-3tn144e 640 1.8v/2.5v/3.3v 113 -3 lead-free tqfp 144 auto lamxo640c-3ftn256e 640 1.8v/2.5v/3.3v 159 -3 lead-free ftbga 256 auto lamxo256e-3tn100e 256 1.2v 78 -3 lead-free tqfp 100 auto lamxo640e-3tn100e 640 1.2v 74 -3 lead-free tqfp 100 auto lamxo640e-3tn144e 640 1.2v 113 -3 lead-free tqfp 144 auto lamxo640e-3ftn256e 640 1.2v 159 -3 lead-free ftbga 256 auto lamxo1200e-3tn100e 1200 1.2v 73 -3 lead-free tqfp 100 auto lamxo1200e-3tn144e 1200 1.2v 113 -3 lead-free tqfp 144 auto lamxo1200e-3ftn256e 1200 1.2v 211 -3 lead-free ftbga 256 auto lamxo2280e-3tn100e 2280 1.2v 73 -3 lead-free tqfp 100 auto lamxo2280e-3tn144e 2280 1.2v 113 -3 lead-free tqfp 144 auto lamxo2280e-3ftn256e 2280 1.2v 211 -3 lead-free ftbga 256 auto lamxo2280e-3ftn324e 2280 1.2v 271 -3 lead-free ftbga 324 auto lamxo xxxx x ?x xxxxxx x grade e = automotive speed 3 = -3 speed grade logic capacity 256 luts = 256 640 luts = 640 1200 luts = 1200 2280 luts = 2280 note: parts dual marked as described. supply voltage c = 1.8v/2.5v/3.3v e = 1.2v package tn100 = 100-pin lead-free tqfp tn144 = 144-pin lead-free tqfp ftn256 = 256-ball lead-free ftbga ftn324 = 324-ball lead-free ftbga device family la-machxo automotive pld la-machxo automotive family data sheet ordering information
november 2007 data sheet ds1003 ?2007 lattice semiconductor corp. all lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www .latticesemi.com/legal. all other brand or product names are trademarks or registered trademarks of their respective holders. the speci?ations and information herein are subject to change without notice. www.latticesemi.com 6-1 ds1003 further information_01.1 for further information a variety of technical notes for the la-machxo family are available on the lattice web site at www .latticesemi.com . ? machxo sysio usage guide (tn1091) ? machxo sysclock pll design and usage guide (tn1089) ? machxo memory usage guide (tn1092) ? power estimation and management for machxo devices (tn1090) ? machxo jtag programming and con?uration users guide (tn1086) minimizing system interruption during con?uration using transfr technology (tn1087) machxo density migration (tn1097) ? ieee 1149.1 boundary scan testability in lattice devices for further information on interface standards refer to the following web sites: ? jedec standards (lvttl, lvcmos): www .jedec.org ?pci: www .pcisig.com la-machxo automotive family data sheet supplemental information
november 2007 data sheet ds1003 ?2007 lattice semiconductor corp. all lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www .latticesemi.com/legal. all other brand or product names are trademarks or registered trademarks of their respective holders. the speci?ations and information herein are subject to change without notice. www.latticesemi.com 7-1 revision history date version section change summary april 2006 01.0 initial release. may 2006 01.1 pinout information removed [loc][0]_pll_rst from signal descriptions table. pclk footnote added to appropriate pins in logic signal connections tables. november 2006 01.2 dc and switching characteristics corrections to machxo ? sleep mode timing table - value for t wsleepn (400ns) changed from max. to min. value for t wawake (100ns) changed from min. to max. added flash download time table. december 2006 01.3 architecture ebr asynchronous reset section added. pinout information power supply and nc table: pin/ball orientation footnotes added. february 2007 01.4 architecture updated ebr asynchronous reset section. november 2007 01.5 dc and switching characteristics updated sysio single-ended dc electrical characteristics table. added jtag port timing waveforms diagram. pinout information added thermal management text section. supplemental information updated title list. la-machxo automotive family data sheet revision history

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